13 Fundamentals of Heat Dissipation in 3D IC Packaging …
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0.55
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0.65
0
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35
3D-MTSV
3D-MTSV
(Cooling)
3D-THiWiNoC
3D-MTSV
3D-THiWiNoC
Flit size (32 bits)
Flit size (256 bits)
Energy cost per bit(nJ)
Peak bandwidth(Tbps)
Peak bandwidth
Energy cost per bit
Fig. 13.7 Peak bandwidth and energy cost per bit for different 3D NoC architectures. Adapted
from [42]
removal of the interlayer TSV based connections across the cooling chip results in
bandwidth degradation by approximately the same amount as the loss in bisectional
bandwidth of the removed TSV based links. On the other hand, for flit size of 256
bits, 3D-MTSV architecture shows nearly 7.6x improvement over flit sizes of 32 bits
whereas in 3D-THiWiNoC architecture, it is about 6.2x. This is because, widening
physical channel width to accommodate larger flit increases data rate of the wireline
links and TSVs. However, the data rate of the wireless links is governed by the speed
of the transceiver and bandwidth of the antennas, which does not change with flit
size. Hence, while the wireline communication becomes faster with increase in flit
size, the wireless communication speed remains constant resulting in lower relative
improvement in bandwidth with increase in flit size compared to a completely wired
NoC. However, wider TSV based vertical links have significant impact on the area
required to route them and consequently, increase the challenges of place and route
of these communication channels across the cooling layers. The interlayer wireless
links alleviates this problem significantly.
The WiNoCs on the other hand can reduce the energy cost per bit compared
to the wireline TSV based 3D NoCs for both flit sizes. It is shown in [30] that
the wireless link is more energy efficient compared to a repeater inserted planar
global wire for distance greater than 7 mm in 65 nm CMOS process. However,
that experiment does not consider any NoC switch or buffering energy overheads,
which can reduce that threshold distance considerably, particularly with high rates
of traffic congestion. Therefore, the energy per bit of 3D-HiWiNoC architecture is
lower than the wired 3D mesh architecture considering the overall effect of NoC
traffic congestions, switch/buffer energy, and the long distance wireless links in the
planar dimensions [41]. Long-range data transfer between different layers of the 3D
NoC between switches, which are separated by several millimeters in the planar
385
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0
5
10
15
20
25
30
35
3D-MTSV
3D-MTSV
(Cooling)
3D-THiWiNoC
3D-MTSV
3D-THiWiNoC
Flit size (32 bits)
Flit size (256 bits)
Energy cost per bit(nJ)
Peak bandwidth(Tbps)
Peak bandwidth
Energy cost per bit
Fig. 13.7 Peak bandwidth and energy cost per bit for different 3D NoC architectures. Adapted
from [42]
removal of the interlayer TSV based connections across the cooling chip results in
bandwidth degradation by approximately the same amount as the loss in bisectional
bandwidth of the removed TSV based links. On the other hand, for flit size of 256
bits, 3D-MTSV architecture shows nearly 7.6x improvement over flit sizes of 32 bits
whereas in 3D-THiWiNoC architecture, it is about 6.2x. This is because, widening
physical channel width to accommodate larger flit increases data rate of the wireline
links and TSVs. However, the data rate of the wireless links is governed by the speed
of the transceiver and bandwidth of the antennas, which does not change with flit
size. Hence, while the wireline communication becomes faster with increase in flit
size, the wireless communication speed remains constant resulting in lower relative
improvement in bandwidth with increase in flit size compared to a completely wired
NoC. However, wider TSV based vertical links have significant impact on the area
required to route them and consequently, increase the challenges of place and route
of these communication channels across the cooling layers. The interlayer wireless
links alleviates this problem significantly.
The WiNoCs on the other hand can reduce the energy cost per bit compared
to the wireline TSV based 3D NoCs for both flit sizes. It is shown in [30] that
the wireless link is more energy efficient compared to a repeater inserted planar
global wire for distance greater than 7 mm in 65 nm CMOS process. However,
that experiment does not consider any NoC switch or buffering energy overheads,
which can reduce that threshold distance considerably, particularly with high rates
of traffic congestion. Therefore, the energy per bit of 3D-HiWiNoC architecture is
lower than the wired 3D mesh architecture considering the overall effect of NoC
traffic congestions, switch/buffer energy, and the long distance wireless links in the
planar dimensions [41]. Long-range data transfer between different layers of the 3D
NoC between switches, which are separated by several millimeters in the planar