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S. G. Kandlikar and A. Ganguly
Moreover, consistently high utilization of all or most cores in a multicore chip results
in high heat dissipation leaving little room for task migrations.
Task migration in 3D multicore environments present its own new set of challenges
due to the smaller footprint of the IC. It is significantly more challenging to find cooler
cores to migrate high power consuming processes given the limited floorplanning
of the 3D ICs. Dynamic voltage frequency scaling (DVFS) is another alternative
technique adopted in multicore processors both in 2D and monolithic 3D platforms
to reduce power consumption and temperature of ICs. In DVFS, the operating voltage
and frequency of the cores of a multicore chip are dynamically adjusted to provide
the minimum power consumption without compromising the overall performance.
It leverages the fact that some process threads can be executed slower than the
maximum speed without delaying the whole task in case those threads do not stall
other threads in the critical path of the program or task running in the system. Recent
works on DVFS for 3D ICs include techniques using an R-C modeling of the heat
dissipation to guide the DVFS decisions [25] and thermally adaptive cache memory
usage to reduce the impact on temperature [26]. Comprehensive thermal management
techniques are developed in [16, 27] where a combined approach utilizing DVFS,
temperature-aware task allocation and liquid cooling is proposed. They also have
overheads for task migrations, context switching and synchronization issues, which
may negatively impact performance. These conventional DTM mechanisms designed
for 2D planar ICs are often not suitable for 3D environments nor are tailored for the
new constraints of monolithic 3D ICs. Consequently, we argue that task migration
based DTM mechanisms are not the most suitable for 3D multicore ICs.
13.6.1 Thermal Considerations in TSV Placements
Another technique to remove the high heat fluxes encountered in 3D ICs is by
deploying Through-Silicon-Vias (TSVs) referred to as thermal vias. The concept
of thermal vias was envisioned for 3D Multichip Modules (MCM) in several publications [28, 29]. It is noted in [29] that while thermal vias can be useful in extracting
heat from monolithic 3D ICs there is a trade-off between the size of the thermal via
islands and the area left for routing. This limits the number and placement options for
the thermal via islands which consist of several individual vias each. Consequently,
placement and optimization techniques, fabrication and packaging methodologies
and Computer Aided Design (CAD) tools that support the deployment of thermal vias
are essential for successfully inserting thermal vias in a monolithic 3D IC to provide
paths for heat extraction. Recently, many works have been proposed to optimize the
location and placement of signal carrying TSVs while being temperature-aware and
mitigating thermal challenges. These use genetic heuristics [30], machine learning
[31] or defect-aware clustering [32, 33].
The overheads of traditional DTM techniques and the challenges of place and
route for thermal vias can be mitigated while providing heat extraction paths using
microfluidic cooling layers for 3D ICs [2, 34]. Cooling 3D ICs has been mainly
S. G. Kandlikar and A. Ganguly
Moreover, consistently high utilization of all or most cores in a multicore chip results
in high heat dissipation leaving little room for task migrations.
Task migration in 3D multicore environments present its own new set of challenges
due to the smaller footprint of the IC. It is significantly more challenging to find cooler
cores to migrate high power consuming processes given the limited floorplanning
of the 3D ICs. Dynamic voltage frequency scaling (DVFS) is another alternative
technique adopted in multicore processors both in 2D and monolithic 3D platforms
to reduce power consumption and temperature of ICs. In DVFS, the operating voltage
and frequency of the cores of a multicore chip are dynamically adjusted to provide
the minimum power consumption without compromising the overall performance.
It leverages the fact that some process threads can be executed slower than the
maximum speed without delaying the whole task in case those threads do not stall
other threads in the critical path of the program or task running in the system. Recent
works on DVFS for 3D ICs include techniques using an R-C modeling of the heat
dissipation to guide the DVFS decisions [25] and thermally adaptive cache memory
usage to reduce the impact on temperature [26]. Comprehensive thermal management
techniques are developed in [16, 27] where a combined approach utilizing DVFS,
temperature-aware task allocation and liquid cooling is proposed. They also have
overheads for task migrations, context switching and synchronization issues, which
may negatively impact performance. These conventional DTM mechanisms designed
for 2D planar ICs are often not suitable for 3D environments nor are tailored for the
new constraints of monolithic 3D ICs. Consequently, we argue that task migration
based DTM mechanisms are not the most suitable for 3D multicore ICs.
13.6.1 Thermal Considerations in TSV Placements
Another technique to remove the high heat fluxes encountered in 3D ICs is by
deploying Through-Silicon-Vias (TSVs) referred to as thermal vias. The concept
of thermal vias was envisioned for 3D Multichip Modules (MCM) in several publications [28, 29]. It is noted in [29] that while thermal vias can be useful in extracting
heat from monolithic 3D ICs there is a trade-off between the size of the thermal via
islands and the area left for routing. This limits the number and placement options for
the thermal via islands which consist of several individual vias each. Consequently,
placement and optimization techniques, fabrication and packaging methodologies
and Computer Aided Design (CAD) tools that support the deployment of thermal vias
are essential for successfully inserting thermal vias in a monolithic 3D IC to provide
paths for heat extraction. Recently, many works have been proposed to optimize the
location and placement of signal carrying TSVs while being temperature-aware and
mitigating thermal challenges. These use genetic heuristics [30], machine learning
[31] or defect-aware clustering [32, 33].
The overheads of traditional DTM techniques and the challenges of place and
route for thermal vias can be mitigated while providing heat extraction paths using
microfluidic cooling layers for 3D ICs [2, 34]. Cooling 3D ICs has been mainly