13 Fundamentals of Heat Dissipation in 3D IC Packaging …
375
13.6 Thermal Design Considerations in 3D IC
Architectures
Three-dimensional Integrated Circuits (3D ICs) have emerged as a feasible solution
to overcome the performance limitations of 2D planar ICs [14]. However, utilizing
the third dimension to provide additional device layers poses thermal challenges as
stacking vertical layers significantly increases the power dissipation density and the
thermal footprint per unit area [15]. One of the major issues in the implementation
of 3D ICs is the excessive heat flux generated by stacking multiple microprocessors,
giving rise to an increase in the power generated per unit surface area as well as in
the peak temperature [16, 17]. While 3D multicore SoCs reduce some of the power
and performance bottlenecks, the increase in power density due to reduced footprint
results in severe thermal issues. These issues lead to higher temperatures requiring
sophisticated cooling technologies. The power density numbers can easily exceed
50 W/cm
2 in 3D ICs which is the limit for forced air cooling [18]. Figure 13.4 shows
the current power density representative of various categories of 3D ICs with data
compiled from the International Technology Roadmap for Semiconductors (ITRS),
2012. Power dissipation densities exceeding 100 W/cm
2 up to 500 W/cm
2 or higher,
are also reported and expected in near future [1]. Such high power dissipation densities can result in quick temperature rises on the chip and cause thermal emergencies. Novel and aggressive cooling techniques are therefore necessary for the heat
extraction in 3D ICs.
Dynamic Thermal Management (DTM) [19–23]. is a widely adopted technique
used to avoid thermal emergencies. One of the most common DTM techniques used
in planar multicore chips is dynamic temperature-aware task migration reallocation
[24]. Several heuristics are proposed over the last several years for achieving optimal
task migration from the perspective of best possible thermal profile of the chip.
Removal of hotspots and maintaining low average chip temperature are among the
chief goals of these heuristics. The underlying principle for all the task migration
heuristics is to move the most high power dissipating processes from hot cores to
relatively cooler cores. However, DTM techniques like task migrations work best to
avoid thermal hotspots when core utilization is sparse with room for task migration.
Fig. 13.4 Trends in power
density trends for various 3D
IC categories
1
10
100
1000
High
Performance
Memory Sensor/Mobile
Devices
Power Density (W/sq. cm)
3D IC Category
375
13.6 Thermal Design Considerations in 3D IC
Architectures
Three-dimensional Integrated Circuits (3D ICs) have emerged as a feasible solution
to overcome the performance limitations of 2D planar ICs [14]. However, utilizing
the third dimension to provide additional device layers poses thermal challenges as
stacking vertical layers significantly increases the power dissipation density and the
thermal footprint per unit area [15]. One of the major issues in the implementation
of 3D ICs is the excessive heat flux generated by stacking multiple microprocessors,
giving rise to an increase in the power generated per unit surface area as well as in
the peak temperature [16, 17]. While 3D multicore SoCs reduce some of the power
and performance bottlenecks, the increase in power density due to reduced footprint
results in severe thermal issues. These issues lead to higher temperatures requiring
sophisticated cooling technologies. The power density numbers can easily exceed
50 W/cm
2 in 3D ICs which is the limit for forced air cooling [18]. Figure 13.4 shows
the current power density representative of various categories of 3D ICs with data
compiled from the International Technology Roadmap for Semiconductors (ITRS),
2012. Power dissipation densities exceeding 100 W/cm
2 up to 500 W/cm
2 or higher,
are also reported and expected in near future [1]. Such high power dissipation densities can result in quick temperature rises on the chip and cause thermal emergencies. Novel and aggressive cooling techniques are therefore necessary for the heat
extraction in 3D ICs.
Dynamic Thermal Management (DTM) [19–23]. is a widely adopted technique
used to avoid thermal emergencies. One of the most common DTM techniques used
in planar multicore chips is dynamic temperature-aware task migration reallocation
[24]. Several heuristics are proposed over the last several years for achieving optimal
task migration from the perspective of best possible thermal profile of the chip.
Removal of hotspots and maintaining low average chip temperature are among the
chief goals of these heuristics. The underlying principle for all the task migration
heuristics is to move the most high power dissipating processes from hot cores to
relatively cooler cores. However, DTM techniques like task migrations work best to
avoid thermal hotspots when core utilization is sparse with room for task migration.
Fig. 13.4 Trends in power
density trends for various 3D
IC categories
1
10
100
1000
High
Performance
Memory Sensor/Mobile
Devices
Power Density (W/sq. cm)
3D IC Category