370
S. G. Kandlikar and A. Ganguly
Fig. 13.1 A schematic of a three layer 3D IC structure with an external heat sink. Redrawn from
[1]
environments such as servers and data centers even if not in systems with stringent form-factor restrictions such as mobile devices. Somewhat less stringent space
restrictions above the chip in the third dimension makes the placement of a heat sink
with air flow passages readily feasible. Such an approach is generally feasible for
a two-chip stack, but introduces severe heat dissipation limits for stacks with three
or more chips. As the heat fluxes in 2D IC chips become large, air cooling is no
longer adequate, and various liquid cooling options such as embedded microchannels [2], spray cooling [3, 4] jet impingement [5] and vapor chamber [6] have been
considered in the literature. Among these, the embedded microchannels, proposed
by Tuckerman and Pease [2] in early eighties have received the greatest attention due
to their compactness, ability to contain the liquid, superior thermal performance in
terms of higher heat dissipation rates, lower pressure drops and higher heat transfer
coefficients. A practical implementation of an IBM silicon chip cooler was demonstrated by Colgan et al. [7] that is capable of addressing the >1 kW/cm
2 cooling
needs. Their chip cooler utilized offset strip fins instead of straight microchannels
to provide lower thermal resistance (determined to be ~1 × 10
− 6 m
2 °C/W) [8].
Kandlikar et al. [9] discuss various cooling options available for 2D and 3D ICs.
As the chips are stacked in a 3D IC package, the placement of the heat sink
becomes possible only above the outermost layer of the 3D IC stack. This approach,
often referred to as conduction cooling, introduces additional thermal resistance for
the interior chips placed in the second layer and further below the directly cooled
chip. The alignment of heat generating devices needs to be carefully evaluated to
avoid localized hot spots created by this stacking effect. Conduction cooling can be
S. G. Kandlikar and A. Ganguly
Fig. 13.1 A schematic of a three layer 3D IC structure with an external heat sink. Redrawn from
[1]
environments such as servers and data centers even if not in systems with stringent form-factor restrictions such as mobile devices. Somewhat less stringent space
restrictions above the chip in the third dimension makes the placement of a heat sink
with air flow passages readily feasible. Such an approach is generally feasible for
a two-chip stack, but introduces severe heat dissipation limits for stacks with three
or more chips. As the heat fluxes in 2D IC chips become large, air cooling is no
longer adequate, and various liquid cooling options such as embedded microchannels [2], spray cooling [3, 4] jet impingement [5] and vapor chamber [6] have been
considered in the literature. Among these, the embedded microchannels, proposed
by Tuckerman and Pease [2] in early eighties have received the greatest attention due
to their compactness, ability to contain the liquid, superior thermal performance in
terms of higher heat dissipation rates, lower pressure drops and higher heat transfer
coefficients. A practical implementation of an IBM silicon chip cooler was demonstrated by Colgan et al. [7] that is capable of addressing the >1 kW/cm
2 cooling
needs. Their chip cooler utilized offset strip fins instead of straight microchannels
to provide lower thermal resistance (determined to be ~1 × 10
− 6 m
2 °C/W) [8].
Kandlikar et al. [9] discuss various cooling options available for 2D and 3D ICs.
As the chips are stacked in a 3D IC package, the placement of the heat sink
becomes possible only above the outermost layer of the 3D IC stack. This approach,
often referred to as conduction cooling, introduces additional thermal resistance for
the interior chips placed in the second layer and further below the directly cooled
chip. The alignment of heat generating devices needs to be carefully evaluated to
avoid localized hot spots created by this stacking effect. Conduction cooling can be