Chapter 13
Fundamentals of Heat Dissipation in 3D
IC Packaging and Thermal-Aware Design
Satish G. Kandlikar and Amlan Ganguly
13.1 Introduction
A schematic of a 3D IC stack is shown in Fig. 13.1. It consists of individual chips
or chip stacks that are separated by cooling layers. In general such 3D integration
is suitable for scenarios that require integration of disparate technologies such as
digital and analog, silicon and non-silicon, electronic and non-electronic in different
layers. As the fabrication facilities required for these technologies as well as their
design constraints may be different, very often, the most efficient way of fabricating
such disparate technologies is to make separate dies for each technology and then
integrate them together in a 3D IC. Due to these benefits, 3D ICs are a method of
choice in such scenarios. However, the major disadvantage of heat dissipation in
these 3D ICs need to be resolved with novel and aggressive cooling technologies
such as active cooling layers inserted between the layers of the 3D IC. The cooling
layer consists of microchannels or finned passages that provide increased surface
area and enhancement for heat transfer from the stack surfaces to the coolant flowing
in the cooling layers. The design of the cooling layer is restricted by the placement of
the through-silicon-vias (TSVs) connecting between adjacent chip stacks. Electrical
and thermal issues require a high degree of co-design for efficient electrical as well
as thermal performance of the 3D ICs.
Using a heat sink and an air cooled fin stack is the most prevalent and cost effective
option available for cooling 2D ICs, particularly in High-Performance Computing
S. G. Kandlikar (B)
Mechanical Engineering Department, Rochester Institute of Technology, Rochester, NY, USA
e-mail: sgkeme@rit.edu
A. Ganguly
Computer Engineering Department, Rochester Institute of Technology, Rochester, NY, USA
e-mail: axgeec@rit.edu
© This is a U.S. government work and not under copyright protection in the U.S.;
foreign copyright protection may apply 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_13
369
Fundamentals of Heat Dissipation in 3D
IC Packaging and Thermal-Aware Design
Satish G. Kandlikar and Amlan Ganguly
13.1 Introduction
A schematic of a 3D IC stack is shown in Fig. 13.1. It consists of individual chips
or chip stacks that are separated by cooling layers. In general such 3D integration
is suitable for scenarios that require integration of disparate technologies such as
digital and analog, silicon and non-silicon, electronic and non-electronic in different
layers. As the fabrication facilities required for these technologies as well as their
design constraints may be different, very often, the most efficient way of fabricating
such disparate technologies is to make separate dies for each technology and then
integrate them together in a 3D IC. Due to these benefits, 3D ICs are a method of
choice in such scenarios. However, the major disadvantage of heat dissipation in
these 3D ICs need to be resolved with novel and aggressive cooling technologies
such as active cooling layers inserted between the layers of the 3D IC. The cooling
layer consists of microchannels or finned passages that provide increased surface
area and enhancement for heat transfer from the stack surfaces to the coolant flowing
in the cooling layers. The design of the cooling layer is restricted by the placement of
the through-silicon-vias (TSVs) connecting between adjacent chip stacks. Electrical
and thermal issues require a high degree of co-design for efficient electrical as well
as thermal performance of the 3D ICs.
Using a heat sink and an air cooled fin stack is the most prevalent and cost effective
option available for cooling 2D ICs, particularly in High-Performance Computing
S. G. Kandlikar (B)
Mechanical Engineering Department, Rochester Institute of Technology, Rochester, NY, USA
e-mail: sgkeme@rit.edu
A. Ganguly
Computer Engineering Department, Rochester Institute of Technology, Rochester, NY, USA
e-mail: axgeec@rit.edu
© This is a U.S. government work and not under copyright protection in the U.S.;
foreign copyright protection may apply 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_13
369