Chapter 12
Fundamentals of Electromigration
in Interconnects of 3D Packaging
Pilin Liu
12.1 Introduction
To meet the demands for higher packaging density, better performance and smaller
form factors, microelectronics industry is currently transitioning from traditional
flip-chip technology to 3D (or 2.5D) integrated circuits (ICs). In 3D ICs, several Si
chips are jointed together by micro-bumps and through Si vias (TSV). Redistribution
layer (RDL) is used in the TSV chip to connect TSV with micro bumps [1, 2]. The
diameter of the micro bumps is about 10–20 μm, which is almost one order of
magnitude smaller than flip chip first level interconnect (FLI). The current density in
micro bumps will increase dramatically with the same power demand and the joule
heating will also be much higher when all the Si chips are stacked together. It can
be seen that EM in micro bumps, TSV and RDL will be a key reliability concern in
3D ICs. High joule heating may also induce large thermal gradient and local high
temperature, inducing thermomigration failure or circuit burn [1–5].
Micro bumps in 3D packaging are Pb-free solder joints with Ni or Cu metallization
[3–5]. The general mechanisms about the EM for larger FLI solder joints will also
apply to the micro bump solder joints. On the other hand, Cu TSV and its connected
metal lines are electroplated Cu. Their EM mechanisms should be very the same as
those for damascene Cu interconnects in Si die.
In this chapter, the general EM factors in solder joints that are applicable to micro
bumps will be briefly summarized in Sect. 12.2, followed by review of the unique EM
behaviors in micro bumps in Sect. 12.3. Thermal migration induced failure modes
will also be included in this section. EM in Cu TSV and its connected metal layers
P. Liu (B)
Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ 85226, USA
e-mail: pilin.liu@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_12
347
Fundamentals of Electromigration
in Interconnects of 3D Packaging
Pilin Liu
12.1 Introduction
To meet the demands for higher packaging density, better performance and smaller
form factors, microelectronics industry is currently transitioning from traditional
flip-chip technology to 3D (or 2.5D) integrated circuits (ICs). In 3D ICs, several Si
chips are jointed together by micro-bumps and through Si vias (TSV). Redistribution
layer (RDL) is used in the TSV chip to connect TSV with micro bumps [1, 2]. The
diameter of the micro bumps is about 10–20 μm, which is almost one order of
magnitude smaller than flip chip first level interconnect (FLI). The current density in
micro bumps will increase dramatically with the same power demand and the joule
heating will also be much higher when all the Si chips are stacked together. It can
be seen that EM in micro bumps, TSV and RDL will be a key reliability concern in
3D ICs. High joule heating may also induce large thermal gradient and local high
temperature, inducing thermomigration failure or circuit burn [1–5].
Micro bumps in 3D packaging are Pb-free solder joints with Ni or Cu metallization
[3–5]. The general mechanisms about the EM for larger FLI solder joints will also
apply to the micro bump solder joints. On the other hand, Cu TSV and its connected
metal lines are electroplated Cu. Their EM mechanisms should be very the same as
those for damascene Cu interconnects in Si die.
In this chapter, the general EM factors in solder joints that are applicable to micro
bumps will be briefly summarized in Sect. 12.2, followed by review of the unique EM
behaviors in micro bumps in Sect. 12.3. Thermal migration induced failure modes
will also be included in this section. EM in Cu TSV and its connected metal layers
P. Liu (B)
Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ 85226, USA
e-mail: pilin.liu@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_12
347