Chapter 2
3D Packaging Architectures
and Assembly Process Design
Ravi Mahajan and Bob Sankman
Acronyms
3D
Three Dimensional
2D
Two Dimensional
SBS
Side by Side
SIP
System in Package
SOC
System on Chip
IP
Intellectual Property
MCP
Multi Chip Package
MCM
Multi Chip Module
MPM
Multi Package Module
EMIB
Embedded Multi-Die Interconnect Bridge
TSV
Through Silicon Via
W2W
Wafer to Wafer
D2W
Die to Wafer
D2D
Die to Die
BI
Burn-In
Tx
Transmitter
Rx
Receiver
TDP
Thermal Design Power
R. Mahajan (B)
Intel Fellow, High Density Interconnect Pathfinding, Assembly Technology, Intel Corporation,
MS CH5-157, 5000 West Chandler Blvd, Chandler, AZ 85226, USA
e-mail: ravi.v.mahajan@intel.com
B. Sankman
Retired Intel Fellow, High Density Interconnect Pathfinding, Assembly Technology, Intel
Corporation, MS CH5-157, 5000 West Chandler Blvd, Chandler, AZ 85226, USA
e-mail: jnjdad1@gmail.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_2
17