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K.-L. Lin
process which involves the melting of solder bump to perform liquid/solid interaction.
Accordingly, the production of the solder bump is the pre-requisite for enabling the
flip chip bonding process. In light of its highest I/O capability the flip chip bonding
technology became the only and must choice for the 3D package technology. The
microbump is a modification basing on the conventional flip chip bump structure.
The conventional flip chip solder bump (or C4 bump, following the original
IBM designed “control collapsed chip connection”) faces the challenge of current
crowding at the entry of electric current to the solder bump. The current crowding
may result in the formation of micro voids which aggregate to form cracks propagating at the interface between the solder bump and the UBM (under bump metal)
layer. A thought in the line of the C4 solder bump design by reducing the bump height
and the UBM area would be a simple approach to produce the microbump. Nevertheless, the miniaturization of the solder joint in the 3D microbump faces the challenge
of increasing current density due to the shrinking contact area. It would largely
reduce the life time as a result of the high current density and the reducing volume
of the microbump. A very promising structure being adopted nowadays, however,
significantly eliminates the influence of current crowding behavior by enlarging the
thickness of the UBM. The Cu UBM of conventional C4 solder bump is now replaced
by Cu pillar in 3D microbump. The thickness of the Cu pillar can be in the range
of 10–30 µm instead of the thin film Cu UBM with shrinking diameter of around
25 µm. The diameters of the Cu pillar and the associated UBM, for example Ti thin
film, on the trace is much smaller than that of the conventional C4 solder bump.
However the high electrical conductivity of Cu and the high volume of the Cu pillar
enable the fast dissipation of the electric current through the Cu pillar so as to avoid
the current crowing at the UBM/solder interface.
Figure 11.1 presents an example of the bumping process [1] for producing
microbump. The process begins with the producing of RDL (redistribution line)
on the chip. The conductive RDL was produced with plating process on the adhesive
and seed layers Ti/Cu. After incorporation of the necessary passive oxide layer, the
Ti/Cu layer were sputtered again as the seed layer for the solder plating. The Cu pillar
and solder, Sn herein this case, were then produced with plating. Appropriate UBM
may also be applied between Cu pillar and solder to reduce Cu consumption. The
solder will be reflowed after plating to form a solder cap for bonding height control.
Figure 11.2 presents the in-line bump and the magnified image of the microbump of
which the bump dimension, including Cu pillar, is less than 10 µm.
The microbumps on chip are bonded to the bonding pad or trace line on the
substrate in the 3D packaging process. There are various structures available for
the substrate metallization. Regardless of the design, the metallization layers on
substrates are mostly following the structures of the conventional C4 substrate or
even the BGA (ball grid array) substrate. These may include OSP (organic solder
preservative) Cu, Cu with barrier layers such as Ni/Pd/Au (ENEPIG, electroless
nickel electroplating palladium immersion gold), etc. The top layers of these structures, either Cu or Au, are not feasible for direct bonding with the Cu pillar. Research
is aiming for Cu to Cu direct bonding. A few options have been proposed and are
being moved towards the larger scale try run. Before the feasible industrial process of
K.-L. Lin
process which involves the melting of solder bump to perform liquid/solid interaction.
Accordingly, the production of the solder bump is the pre-requisite for enabling the
flip chip bonding process. In light of its highest I/O capability the flip chip bonding
technology became the only and must choice for the 3D package technology. The
microbump is a modification basing on the conventional flip chip bump structure.
The conventional flip chip solder bump (or C4 bump, following the original
IBM designed “control collapsed chip connection”) faces the challenge of current
crowding at the entry of electric current to the solder bump. The current crowding
may result in the formation of micro voids which aggregate to form cracks propagating at the interface between the solder bump and the UBM (under bump metal)
layer. A thought in the line of the C4 solder bump design by reducing the bump height
and the UBM area would be a simple approach to produce the microbump. Nevertheless, the miniaturization of the solder joint in the 3D microbump faces the challenge
of increasing current density due to the shrinking contact area. It would largely
reduce the life time as a result of the high current density and the reducing volume
of the microbump. A very promising structure being adopted nowadays, however,
significantly eliminates the influence of current crowding behavior by enlarging the
thickness of the UBM. The Cu UBM of conventional C4 solder bump is now replaced
by Cu pillar in 3D microbump. The thickness of the Cu pillar can be in the range
of 10–30 µm instead of the thin film Cu UBM with shrinking diameter of around
25 µm. The diameters of the Cu pillar and the associated UBM, for example Ti thin
film, on the trace is much smaller than that of the conventional C4 solder bump.
However the high electrical conductivity of Cu and the high volume of the Cu pillar
enable the fast dissipation of the electric current through the Cu pillar so as to avoid
the current crowing at the UBM/solder interface.
Figure 11.1 presents an example of the bumping process [1] for producing
microbump. The process begins with the producing of RDL (redistribution line)
on the chip. The conductive RDL was produced with plating process on the adhesive
and seed layers Ti/Cu. After incorporation of the necessary passive oxide layer, the
Ti/Cu layer were sputtered again as the seed layer for the solder plating. The Cu pillar
and solder, Sn herein this case, were then produced with plating. Appropriate UBM
may also be applied between Cu pillar and solder to reduce Cu consumption. The
solder will be reflowed after plating to form a solder cap for bonding height control.
Figure 11.2 presents the in-line bump and the magnified image of the microbump of
which the bump dimension, including Cu pillar, is less than 10 µm.
The microbumps on chip are bonded to the bonding pad or trace line on the
substrate in the 3D packaging process. There are various structures available for
the substrate metallization. Regardless of the design, the metallization layers on
substrates are mostly following the structures of the conventional C4 substrate or
even the BGA (ball grid array) substrate. These may include OSP (organic solder
preservative) Cu, Cu with barrier layers such as Ni/Pd/Au (ENEPIG, electroless
nickel electroplating palladium immersion gold), etc. The top layers of these structures, either Cu or Au, are not feasible for direct bonding with the Cu pillar. Research
is aiming for Cu to Cu direct bonding. A few options have been proposed and are
being moved towards the larger scale try run. Before the feasible industrial process of