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S. Lee
flux and underfill beyond its limits. To accommodate the rapid process cycle, revolutionary changes in material formulations are required for the flux and underfill
materials, directly affecting assembly yield and reliability performance.
The details of the TCB process are as follows: the bond head has an integrated
heater that will compress a die to material dispensed on the bonding site or material
pre-applied die to the bonding site, while simultaneously ramping the temperature
of head up above solder melting point. Then the head cools down heater and bonded
backage to a temperature, just below solder solidification point as fast as possible.
Note that the ramp rate of the TCB head typically is 100 °C/s and the rate of mass
reflow process is at most 2.0 °C/s. When reaching the a lower setting temperature, the bond head disengages from a package and a bonding cycle is complete.
Even with consideration of TCB ramp rate only, the challenges are obvious for
the packaging industry to demonstrate 3D packages technology including assembly
processes, materials, and equipment. Due to the aforementioned technical challenges,
the placement accuracy requirement is coupled with a very rapidly changing thermal
process, it is clear that TCB will be the most difficult process step out of 3D package
assembly processes. Even though the TCB is a fast assembly process, the process
will be a bottleneck restricting overall throughput because a unit will be processed
individually. The resultant of low throughput would pose a cost disadvantage in 3D
packages.
Therefore, this chapter will review the TCB technique including process tolerances, principles of process materials, and assembly methods, where limited literature resources exist at the present time. In addition, the chapter would provide readers
with insight of how to design process building blocks that are relevant to their products. Detailed discussion include how to select materials that are compatible with the
chosen building block in terms of processability, reliability, and throughput. In other
words, this chapter will explore engineering sciences and fundamentals required for
an enabler of 3D electronic packaging [1–10].
10.2 Background
In the current semiconductor industry, 3D packaging implies interconnection technology using Through Silicon Vias (TSV) technology. The technology can shorten
vertical interconnects, replacing the long electrical paths in 2D packaging, to improve
electrical performance or to reduce timing delay. The TSV idea was firstly introduced
in 1962 and products adopting the TSV technology appeared to electronic industry
in 2014. Even now, the packaging industry still faces technical challenges such as
substantially low throughput resulting from premature building blocks associated
with process materials and electrical performance drop due to heat dissipation issues.
A complicated supply chain in TSV industry amplifies these technical challenges.
All building blocks currently under investigation for 2.5/3D packages have
selected TCB technology to meet the placement accuracy requirements of fine pitch
flip chip stacking of thin TSV micro-bumped die. The thin die (<100 μm) may
S. Lee
flux and underfill beyond its limits. To accommodate the rapid process cycle, revolutionary changes in material formulations are required for the flux and underfill
materials, directly affecting assembly yield and reliability performance.
The details of the TCB process are as follows: the bond head has an integrated
heater that will compress a die to material dispensed on the bonding site or material
pre-applied die to the bonding site, while simultaneously ramping the temperature
of head up above solder melting point. Then the head cools down heater and bonded
backage to a temperature, just below solder solidification point as fast as possible.
Note that the ramp rate of the TCB head typically is 100 °C/s and the rate of mass
reflow process is at most 2.0 °C/s. When reaching the a lower setting temperature, the bond head disengages from a package and a bonding cycle is complete.
Even with consideration of TCB ramp rate only, the challenges are obvious for
the packaging industry to demonstrate 3D packages technology including assembly
processes, materials, and equipment. Due to the aforementioned technical challenges,
the placement accuracy requirement is coupled with a very rapidly changing thermal
process, it is clear that TCB will be the most difficult process step out of 3D package
assembly processes. Even though the TCB is a fast assembly process, the process
will be a bottleneck restricting overall throughput because a unit will be processed
individually. The resultant of low throughput would pose a cost disadvantage in 3D
packages.
Therefore, this chapter will review the TCB technique including process tolerances, principles of process materials, and assembly methods, where limited literature resources exist at the present time. In addition, the chapter would provide readers
with insight of how to design process building blocks that are relevant to their products. Detailed discussion include how to select materials that are compatible with the
chosen building block in terms of processability, reliability, and throughput. In other
words, this chapter will explore engineering sciences and fundamentals required for
an enabler of 3D electronic packaging [1–10].
10.2 Background
In the current semiconductor industry, 3D packaging implies interconnection technology using Through Silicon Vias (TSV) technology. The technology can shorten
vertical interconnects, replacing the long electrical paths in 2D packaging, to improve
electrical performance or to reduce timing delay. The TSV idea was firstly introduced
in 1962 and products adopting the TSV technology appeared to electronic industry
in 2014. Even now, the packaging industry still faces technical challenges such as
substantially low throughput resulting from premature building blocks associated
with process materials and electrical performance drop due to heat dissipation issues.
A complicated supply chain in TSV industry amplifies these technical challenges.
All building blocks currently under investigation for 2.5/3D packages have
selected TCB technology to meet the placement accuracy requirements of fine pitch
flip chip stacking of thin TSV micro-bumped die. The thin die (<100 μm) may