4
Y. Li and D. Goyal
This chapter provides detailed illustration of motivations as well as various
architectures of 3D packaging. Challenges in 3D packaging, including fabrication,
assembly, cost, design, modeling, thermal management, material, substrate, quality,
reliability, and failure analysis, are reviewed with brief introduction to the chapters
addressing these challenges.
1.2 Why 3D Packaging
1.2.1 Moore’s Law
Since Intel introduced the world’s first single-chip microprocessor, the Intel 4004,
in 1971, an exponential growth of ICs has been observed following Moore’s law in
terms of transistor number per chip [12]. As illustrated in Fig. 1.5, the number of
transistors per Si chip doubles approximately every 18 months, resulting in a straight
line on a log scale [12, 13]. In 1990, the bipolar transistor technology switched to
CMOS in order to reduce thermal power, circuit size, and manufacturing costs, at the
same time increase the operating speed and energy efficiency [3]. In the early 2000s,
multi-core processors were developed to address the challenging thermal power issue
in conventional single-core processors [3]. Since multicore processors require enormous cache capacity and memory bandwidth to achieve the designed performance,
3D packaging becomes one of the viable solutions to provide the required cache and
bandwidth with a relatively low cost [3].
Fig. 1.5 Moore’s law
predicts the exponential
growth of ICs since 1970s
(Adapted from Ref. [13])
Y. Li and D. Goyal
This chapter provides detailed illustration of motivations as well as various
architectures of 3D packaging. Challenges in 3D packaging, including fabrication,
assembly, cost, design, modeling, thermal management, material, substrate, quality,
reliability, and failure analysis, are reviewed with brief introduction to the chapters
addressing these challenges.
1.2 Why 3D Packaging
1.2.1 Moore’s Law
Since Intel introduced the world’s first single-chip microprocessor, the Intel 4004,
in 1971, an exponential growth of ICs has been observed following Moore’s law in
terms of transistor number per chip [12]. As illustrated in Fig. 1.5, the number of
transistors per Si chip doubles approximately every 18 months, resulting in a straight
line on a log scale [12, 13]. In 1990, the bipolar transistor technology switched to
CMOS in order to reduce thermal power, circuit size, and manufacturing costs, at the
same time increase the operating speed and energy efficiency [3]. In the early 2000s,
multi-core processors were developed to address the challenging thermal power issue
in conventional single-core processors [3]. Since multicore processors require enormous cache capacity and memory bandwidth to achieve the designed performance,
3D packaging becomes one of the viable solutions to provide the required cache and
bandwidth with a relatively low cost [3].
Fig. 1.5 Moore’s law
predicts the exponential
growth of ICs since 1970s
(Adapted from Ref. [13])