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T. Suga et al.
Al oxide, Cu oxide growth is not self-limiting, hence grows thicker than traditional Aluminum oxide and requires cleaning treatment to generate pristine Cu
surfaces suitable for bonding. Depending on the bonding environment (vacuum,
inert, reducing, or ambient atmosphere), surface preparation and passivation, and
handling of warpage and flatness, Cu–Cu bonding processes have been demonstrated
at temperatures lower than the usual lead-free solder melting temperatures, down
to 100–150 °C range with some demonstrations also down to room temperature.
Variants of the Cu–Cu bonding processes include: thermo-compression bonding (an
example of diffusion bonding), surface activated bonding (SAB), Cu–Cu bonding
with assist processes (surface cleaning, treatment, and passivation with noble and
non-noble capping layers), and hybrid bonding and insertion bonding. We will revisit
such process conditions in more details in subsequent sections of this chapter.
8.3 Stacking and Bonding Schemes, Technologies
and Applications
Stacking and bonding schemes and technologies are classified based on the form
factor of bonding surfaces, the geometry and topology of the active electronic devices
and packages and target applications. With respect to form factor, processes are distinguished as chip-on-chip (CoC), chip-on-wafer (CoW) or wafer-on-wafer (WoW).
Benefits of the CoC and CoW bonding schemes include use of known-good-dies
(KGD’s
3 ) for high yield and integration of chips of different sizes with high flexibility. However, the disadvantages are low throughput (especially CoC) and low
alignment accuracy. WoW enables high throughput and high alignment accuracy,
however it suffers from yield loss (“fall out”) due to lack of KGD’s and inflexibility
with different sizes of stacked layers. To solve these drawbacks, multi-CoW bonding
has been developed for bonding of multiple chips temporary assembled on a carrier
wafer (e.g., through liquid-assisted self-assembly [11]) onto a wafer.
Bonding schemes can also be distinguished based on how the active surfaces
(having devices) are brought into contact, e.g. face-to-face (F2F), and back-to-face
(B2F) or face-to-back (F2B) and back-to-back (B2B). The face side refers to the front
side of wafers where active devices are fabricated; backside refers to the opposite side
of the face side and is usually obtained after thinning and insulation/metallization.
In case of passive silicon interposer that has no active devices, the surface processed
first is commonly termed as face side and the opposite as backside. F2F bonding uses
Cu pads on the top metal layer above the active devices, and wafers are brought into
contact between the face sides of both wafers, as illustrated in Fig. 8.2a. F2F bonding
is widely used for two-layer 3D stacking. Morrow et al. [3] at Intel employed F2F
bonding for 3D stacking of wafers having active devices such as 65-nm MOSFETs
and 4-MB SRAMs using Cu bonding pads with size ranging between 5 μm × 5 μm
and 6 μm × 40 μm. Subsequently, one of the F2F bonded wafers can be thinned
3 Pre-tested and sorted chips, hence the nomenclature: “known good dies” (KGD’s)
T. Suga et al.
Al oxide, Cu oxide growth is not self-limiting, hence grows thicker than traditional Aluminum oxide and requires cleaning treatment to generate pristine Cu
surfaces suitable for bonding. Depending on the bonding environment (vacuum,
inert, reducing, or ambient atmosphere), surface preparation and passivation, and
handling of warpage and flatness, Cu–Cu bonding processes have been demonstrated
at temperatures lower than the usual lead-free solder melting temperatures, down
to 100–150 °C range with some demonstrations also down to room temperature.
Variants of the Cu–Cu bonding processes include: thermo-compression bonding (an
example of diffusion bonding), surface activated bonding (SAB), Cu–Cu bonding
with assist processes (surface cleaning, treatment, and passivation with noble and
non-noble capping layers), and hybrid bonding and insertion bonding. We will revisit
such process conditions in more details in subsequent sections of this chapter.
8.3 Stacking and Bonding Schemes, Technologies
and Applications
Stacking and bonding schemes and technologies are classified based on the form
factor of bonding surfaces, the geometry and topology of the active electronic devices
and packages and target applications. With respect to form factor, processes are distinguished as chip-on-chip (CoC), chip-on-wafer (CoW) or wafer-on-wafer (WoW).
Benefits of the CoC and CoW bonding schemes include use of known-good-dies
(KGD’s
3 ) for high yield and integration of chips of different sizes with high flexibility. However, the disadvantages are low throughput (especially CoC) and low
alignment accuracy. WoW enables high throughput and high alignment accuracy,
however it suffers from yield loss (“fall out”) due to lack of KGD’s and inflexibility
with different sizes of stacked layers. To solve these drawbacks, multi-CoW bonding
has been developed for bonding of multiple chips temporary assembled on a carrier
wafer (e.g., through liquid-assisted self-assembly [11]) onto a wafer.
Bonding schemes can also be distinguished based on how the active surfaces
(having devices) are brought into contact, e.g. face-to-face (F2F), and back-to-face
(B2F) or face-to-back (F2B) and back-to-back (B2B). The face side refers to the front
side of wafers where active devices are fabricated; backside refers to the opposite side
of the face side and is usually obtained after thinning and insulation/metallization.
In case of passive silicon interposer that has no active devices, the surface processed
first is commonly termed as face side and the opposite as backside. F2F bonding uses
Cu pads on the top metal layer above the active devices, and wafers are brought into
contact between the face sides of both wafers, as illustrated in Fig. 8.2a. F2F bonding
is widely used for two-layer 3D stacking. Morrow et al. [3] at Intel employed F2F
bonding for 3D stacking of wafers having active devices such as 65-nm MOSFETs
and 4-MB SRAMs using Cu bonding pads with size ranging between 5 μm × 5 μm
and 6 μm × 40 μm. Subsequently, one of the F2F bonded wafers can be thinned
3 Pre-tested and sorted chips, hence the nomenclature: “known good dies” (KGD’s)