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T. Suga et al.
reflow or thermo-compression bonding (TCB) in the temperature range of 250–
275 °C, the Cu–Cu bonding process should target lower temperature range (from
room temperature to 250 °C).
1
The study of Cu–Cu bonding as a method for interconnection started in universities around the world approximately in year 2000 [1, 2], soon after the announcement
of Cu interconnects for integrated circuits by IBM in the late ‘90s. For high-density
interconnects (HDI), Cu–Cu bonding has been demonstrated since 2006 by Morrow
et al. [3] of Intel (with 5 × 5 μm
2 Cu pads) and by Suga’s group [4] at the University of Tokyo (with ~3 μm diameter Cu pads) respectively. For 3D stacking in case
of extremely thinned dies with 10 μm pitch TSVs, bonding has been demonstrated
also in 2006 by Swinnen et al. at IMEC [5]. Cu–Cu bonding for 3D prototypes such
as memories, sensors, processors, and memory/processor stacks has been demonstrated by Intel [3] and Tezzaron [6]. Cu/SiO 2 hybrid bonding by Ziptronix
2 has also
been demonstrated in a 3D stacking configuration by Fermilab [7, 8], Sony [9], and
Tezzaron/Novati.
In summary, in this chapter, we introduce the pros and cons of Cu–Cu bonding and
stacking/bonding schemes for different applications. We review various methods of
Cu–Cu bonding: (a) thermo-compression bonding (an example of diffusion bonding),
(b) Cu–Cu bonding with passivation capping layers, (c) surface activated bonding
(SAB), and (d) alternative bonding methods (e.g. Cu/dielectric hybrid and Cu–
Cu insertion bonding). We also discuss the effects of surface activation, surface
microstructures, surface characteristics, and surface passivation for Cu–Cu bonding
to understand how bonding behavior depends on Cu surface cleanness, diffusion,
temperature, compression pressure, and bonding atmosphere. Lastly, we summarize
the state-of-the-art and recommendations for future directions.
8.2 Solder-Based versus Solder-Less Bonding: Pros
and Cons
Solder-based bonding is prevalent in 3D interconnects usually employing one-sided
scheme of solder microbump (e.g. Cu/x/solder, where x would be a diffusion barrier
like Ni (or no barrier at all) and solder would be SnAg, SnCu or other binary
solder (e.g. typically electroplated) bonded on metal pad (e.g. Cu with a passivation
layer or other capping layer, or pre-cleaned/pre-treated to prevent/remove oxidation). The key advantages of solder-based schemes are process robustness given that
1 Process times targets depend on stacking process e.g. chip-on-chip (CoC), chip-on-wafer (CoW)
or wafer-on-wafer (WoW) processes, equipment configuration and manufacturing embodiment and
resulting throughput and Model of Record (MoR). For Cu–Cu process to be adopted in high-volume
manufacturing (HVM), higher throughput and lower cost is required compared to established (and
depreciated) solder-based processes.
2 Acquired by Tessera, now consolidated in Xperi and TiVo merger end of 2019.
T. Suga et al.
reflow or thermo-compression bonding (TCB) in the temperature range of 250–
275 °C, the Cu–Cu bonding process should target lower temperature range (from
room temperature to 250 °C).
1
The study of Cu–Cu bonding as a method for interconnection started in universities around the world approximately in year 2000 [1, 2], soon after the announcement
of Cu interconnects for integrated circuits by IBM in the late ‘90s. For high-density
interconnects (HDI), Cu–Cu bonding has been demonstrated since 2006 by Morrow
et al. [3] of Intel (with 5 × 5 μm
2 Cu pads) and by Suga’s group [4] at the University of Tokyo (with ~3 μm diameter Cu pads) respectively. For 3D stacking in case
of extremely thinned dies with 10 μm pitch TSVs, bonding has been demonstrated
also in 2006 by Swinnen et al. at IMEC [5]. Cu–Cu bonding for 3D prototypes such
as memories, sensors, processors, and memory/processor stacks has been demonstrated by Intel [3] and Tezzaron [6]. Cu/SiO 2 hybrid bonding by Ziptronix
2 has also
been demonstrated in a 3D stacking configuration by Fermilab [7, 8], Sony [9], and
Tezzaron/Novati.
In summary, in this chapter, we introduce the pros and cons of Cu–Cu bonding and
stacking/bonding schemes for different applications. We review various methods of
Cu–Cu bonding: (a) thermo-compression bonding (an example of diffusion bonding),
(b) Cu–Cu bonding with passivation capping layers, (c) surface activated bonding
(SAB), and (d) alternative bonding methods (e.g. Cu/dielectric hybrid and Cu–
Cu insertion bonding). We also discuss the effects of surface activation, surface
microstructures, surface characteristics, and surface passivation for Cu–Cu bonding
to understand how bonding behavior depends on Cu surface cleanness, diffusion,
temperature, compression pressure, and bonding atmosphere. Lastly, we summarize
the state-of-the-art and recommendations for future directions.
8.2 Solder-Based versus Solder-Less Bonding: Pros
and Cons
Solder-based bonding is prevalent in 3D interconnects usually employing one-sided
scheme of solder microbump (e.g. Cu/x/solder, where x would be a diffusion barrier
like Ni (or no barrier at all) and solder would be SnAg, SnCu or other binary
solder (e.g. typically electroplated) bonded on metal pad (e.g. Cu with a passivation
layer or other capping layer, or pre-cleaned/pre-treated to prevent/remove oxidation). The key advantages of solder-based schemes are process robustness given that
1 Process times targets depend on stacking process e.g. chip-on-chip (CoC), chip-on-wafer (CoW)
or wafer-on-wafer (WoW) processes, equipment configuration and manufacturing embodiment and
resulting throughput and Model of Record (MoR). For Cu–Cu process to be adopted in high-volume
manufacturing (HVM), higher throughput and lower cost is required compared to established (and
depreciated) solder-based processes.
2 Acquired by Tessera, now consolidated in Xperi and TiVo merger end of 2019.