Chapter 8
Direct Cu to Cu Bonding and Alternative
Bonding Techniques in 3D Packaging
Tadatomo Suga, Ran He, George Vakanas, and Antonio La Manna
8.1 Introduction
Reliable, high-throughput, low-cost, low-temperature bonding processes have always
been in high demand in industrial, electronics and semiconductor manufacturing.
Multiple techniques and processes have been demonstrated in different domain
applications, with distinct advantages and disadvantages that we will explore in
this chapter. With the trend towards further device scaling and applications-driven
roadmaps, three-dimensional (3D) integration has evolved with bandwidth, power,
performance, and form factor advantages over planar, side-by-side, electronic packaging architecture. To enable 3D technology, high-density interconnects (sub-40 um
pitch) and high-throughput and reliable stacking/bonding processes are required.
Cu–Cu bonding is a promising candidate as a 3D interconnect method, since Cu is a
well-studied and well-understood metallurgy for back-end-of-line (BEOL) layers and
for through-silicon vias (TSVs). Cu also offers mechanical, electrical, and thermal
advantages based on its material properties compared to aluminum, transition metals
and noble metals. Comparing to solder-based pillar/bump processes with solder
T. Suga · R. He
The University of Tokyo, Tokyo, Japan
G. Vakanas (B)
Intel Corporation, Santa Clara, CA, USA
e-mail: george.p.vakanas@intel.com
A. La Manna
IMEC, Louvain, Belgium
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_8
201
Direct Cu to Cu Bonding and Alternative
Bonding Techniques in 3D Packaging
Tadatomo Suga, Ran He, George Vakanas, and Antonio La Manna
8.1 Introduction
Reliable, high-throughput, low-cost, low-temperature bonding processes have always
been in high demand in industrial, electronics and semiconductor manufacturing.
Multiple techniques and processes have been demonstrated in different domain
applications, with distinct advantages and disadvantages that we will explore in
this chapter. With the trend towards further device scaling and applications-driven
roadmaps, three-dimensional (3D) integration has evolved with bandwidth, power,
performance, and form factor advantages over planar, side-by-side, electronic packaging architecture. To enable 3D technology, high-density interconnects (sub-40 um
pitch) and high-throughput and reliable stacking/bonding processes are required.
Cu–Cu bonding is a promising candidate as a 3D interconnect method, since Cu is a
well-studied and well-understood metallurgy for back-end-of-line (BEOL) layers and
for through-silicon vias (TSVs). Cu also offers mechanical, electrical, and thermal
advantages based on its material properties compared to aluminum, transition metals
and noble metals. Comparing to solder-based pillar/bump processes with solder
T. Suga · R. He
The University of Tokyo, Tokyo, Japan
G. Vakanas (B)
Intel Corporation, Santa Clara, CA, USA
e-mail: george.p.vakanas@intel.com
A. La Manna
IMEC, Louvain, Belgium
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_8
201