7 Fundamentals and Failures in Die Preparation for 3D Packaging
195
11. M. Shungwu, D. Pang, S. Nathapong, P. Marimuthu, Temporary bonding of wafer to carrier for
3D-wafer level packaging, in Electronics Packaging Technologies Conference, pp. 405–411
(2008)
12. J. Charbonnier, S. Cheramy, D. Henry, A. Astier, J. Brun, N. Sillon, Integration of a temporary
carrier in a TSV process flow, in Electronic Components and Technology Conference, pp. 865–
871 (2009)
13. S. Pargfrieder, J. Burggraf, D. Burgstaller, M. Privett, A. Jouve, D. Henry, N. Sillon, 3D
integration with TSV: temporary bonding and debonding. Solid State Technol. 3, 38–43 (2009)
14. J. Gambino, Thin silicon wafer processing and strength characterization, in 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 199–207
(2013)
15. M. Grief, J. Steele Jr., Warpage and mechanical strength studies of ultra thin 150 mm wafers,
in IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, pp. 190–194 (1996)
16. W. Kroninger, F. Mariani, Thinning and singulation of silicon: root causes of the damage in
thin chips, in Electronic Components and Technology Conference, pp. 1317–1322 (2006)
17. S. Chen, I. Shih, Y. Chen, C. Tsai, J. Lin, E. Wu, How to improve chip strength to avoid die
cracking in a package, in IEEE Inter Society Conference on Thermal Phenomena, pp. 268–273
(2004)
18. V. Sheng, N. Khan, D. Kripesh, Y. UK, Ultra thinning of wafer for embedded module, in
IEEE Electronics Packaging Technology Conference, pp. 837–842 (2006)
19. L. Wetz, J. White, B. Keser, Improvement in WL-CSP reliability by wafer thinning, in
Electronic Components and Technology Conference, pp. 853–856 (2003)
20. S. Farrens, Wafer and die bonding technologies for 3D integration, in MRS Fall 2008
Proceedings E
21. L. Marinier, W. Noort, R. Pellens, B. Sutedja, R. Dekker, H. Zeijl, Front- to back-side overlay
optimization after wafer bonding for 3D integration. Microelectron. Eng. 83, 1229–1232
(2006)
22. H. Shi, H. Huang, J. Bao, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser, Plasma
altered layer model for plasma damage characterization of porous OSG films, in IEEE
Internationa Interconnect Technology Conference, pp. 78–80 (2009)
23. H. Shi, H. Huang, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser, Minimization of plasma ashing damage to OSG low-k dielectrics, in IEEE International Interconnect
Technology Conference, pp. 1–3 (2010)
24. H. Shi, Mechanistic study of plasma damage to porous low-k: process development and
dielectric recover, Ph.D. Dissertation, The University of Texas at Austin, 2010
25. C. Cassidy, F. Renz, J. Kraft, F. Schrank, Depth-resolved photoemission microscopy for
localization of leakage currents in through Silicon Vias (TSVs), in 16th IEEE International
Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 35–740 (2009)
26. Y. Mizushima, H. Kitada, K. Koshikawa, S. Suzuki, T. Nakamura, T. Ohba, Novel through
silicon vias leakage current evaluation using infrared-optical beam irradiation. Jpn. J. Appl.
Phys. 51(5S) (2012)
27. N. Ranganathan, D. Lee, L. Youhe, G. Lo, K. Prasad, K. Pey, N. Ranganathan, D. Lee, L.
Youhe, G. Lo, K. Prasad, K. Pey, Influence of Bosch etch process on electrical isolation of
TSV structures. IEEE Trans. Compon. Packag. Manuf. Technol. 1(10), 1497–1507 (2011)
28. T. Nakamura, H. Kitada, Y. Mizushima, N. Maeda, K. Fujimoto, T. Ohba, Comparative study
of side-wall roughness effects on leakage currents in through-silicon via interconnects, in
2011 IEEE International 3D Systems Integration Conference (3DIC), pp. 1–4, (2012)
29. J. Lin, W. Chiou, K. Yang, H. Chang, Y. Lin, E. Liao, J. Hung, Y. Lin, P. Tsai, Y. Shih, T. Wu,
W. Wu, F. Tsai, Y. Huang, T. Wang, C. Yu, C. Chang, M. Chen, S. Hou, C. Tung, S. Jeng,
D. Yu, High density 3D integration using CMOS foundry technologies for 28 nm node and
beyond, in IEEE International Electron Devices Meeting (IEDM), pp. 2.1.1–2.1.4 (2010)
30. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, R. Tummala, Electrical
modeling of through silicon and package vias, in IEEE International Conference on 3D
System Integration, pp. 1–8 (2009)
195
11. M. Shungwu, D. Pang, S. Nathapong, P. Marimuthu, Temporary bonding of wafer to carrier for
3D-wafer level packaging, in Electronics Packaging Technologies Conference, pp. 405–411
(2008)
12. J. Charbonnier, S. Cheramy, D. Henry, A. Astier, J. Brun, N. Sillon, Integration of a temporary
carrier in a TSV process flow, in Electronic Components and Technology Conference, pp. 865–
871 (2009)
13. S. Pargfrieder, J. Burggraf, D. Burgstaller, M. Privett, A. Jouve, D. Henry, N. Sillon, 3D
integration with TSV: temporary bonding and debonding. Solid State Technol. 3, 38–43 (2009)
14. J. Gambino, Thin silicon wafer processing and strength characterization, in 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 199–207
(2013)
15. M. Grief, J. Steele Jr., Warpage and mechanical strength studies of ultra thin 150 mm wafers,
in IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, pp. 190–194 (1996)
16. W. Kroninger, F. Mariani, Thinning and singulation of silicon: root causes of the damage in
thin chips, in Electronic Components and Technology Conference, pp. 1317–1322 (2006)
17. S. Chen, I. Shih, Y. Chen, C. Tsai, J. Lin, E. Wu, How to improve chip strength to avoid die
cracking in a package, in IEEE Inter Society Conference on Thermal Phenomena, pp. 268–273
(2004)
18. V. Sheng, N. Khan, D. Kripesh, Y. UK, Ultra thinning of wafer for embedded module, in
IEEE Electronics Packaging Technology Conference, pp. 837–842 (2006)
19. L. Wetz, J. White, B. Keser, Improvement in WL-CSP reliability by wafer thinning, in
Electronic Components and Technology Conference, pp. 853–856 (2003)
20. S. Farrens, Wafer and die bonding technologies for 3D integration, in MRS Fall 2008
Proceedings E
21. L. Marinier, W. Noort, R. Pellens, B. Sutedja, R. Dekker, H. Zeijl, Front- to back-side overlay
optimization after wafer bonding for 3D integration. Microelectron. Eng. 83, 1229–1232
(2006)
22. H. Shi, H. Huang, J. Bao, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser, Plasma
altered layer model for plasma damage characterization of porous OSG films, in IEEE
Internationa Interconnect Technology Conference, pp. 78–80 (2009)
23. H. Shi, H. Huang, J. Im, P. Ho, Y. Zhou, J. Pender, M. Armacost, D. Kyser, Minimization of plasma ashing damage to OSG low-k dielectrics, in IEEE International Interconnect
Technology Conference, pp. 1–3 (2010)
24. H. Shi, Mechanistic study of plasma damage to porous low-k: process development and
dielectric recover, Ph.D. Dissertation, The University of Texas at Austin, 2010
25. C. Cassidy, F. Renz, J. Kraft, F. Schrank, Depth-resolved photoemission microscopy for
localization of leakage currents in through Silicon Vias (TSVs), in 16th IEEE International
Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 35–740 (2009)
26. Y. Mizushima, H. Kitada, K. Koshikawa, S. Suzuki, T. Nakamura, T. Ohba, Novel through
silicon vias leakage current evaluation using infrared-optical beam irradiation. Jpn. J. Appl.
Phys. 51(5S) (2012)
27. N. Ranganathan, D. Lee, L. Youhe, G. Lo, K. Prasad, K. Pey, N. Ranganathan, D. Lee, L.
Youhe, G. Lo, K. Prasad, K. Pey, Influence of Bosch etch process on electrical isolation of
TSV structures. IEEE Trans. Compon. Packag. Manuf. Technol. 1(10), 1497–1507 (2011)
28. T. Nakamura, H. Kitada, Y. Mizushima, N. Maeda, K. Fujimoto, T. Ohba, Comparative study
of side-wall roughness effects on leakage currents in through-silicon via interconnects, in
2011 IEEE International 3D Systems Integration Conference (3DIC), pp. 1–4, (2012)
29. J. Lin, W. Chiou, K. Yang, H. Chang, Y. Lin, E. Liao, J. Hung, Y. Lin, P. Tsai, Y. Shih, T. Wu,
W. Wu, F. Tsai, Y. Huang, T. Wang, C. Yu, C. Chang, M. Chen, S. Hou, C. Tung, S. Jeng,
D. Yu, High density 3D integration using CMOS foundry technologies for 28 nm node and
beyond, in IEEE International Electron Devices Meeting (IEDM), pp. 2.1.1–2.1.4 (2010)
30. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, R. Tummala, Electrical
modeling of through silicon and package vias, in IEEE International Conference on 3D
System Integration, pp. 1–8 (2009)