194
H. Ma et al.
should be increased while the epoxy weight (M) and epoxy contact angel at substrate
(θ ) should be reduced.
7.10 Conclusions
In summary, we briefly overviewed the general TSV wafer fabrication processes and
dived into the fundamentals and failures of temporary wafer bonding and debonding,
laser scribe, wafer saw dicing, die pick and place, chip attach and underfill processes.
Understanding the temporary wafer bonding and debonding and die preparation
process mechanisms and fundamentals is key to deliver a high yield and reliable
process for 3D packaging.
Acknowledgements The authors would like to acknowledge Dr. Sairam Agraharam and Dr. Jay
Cheng of Intel Corp. for valuable discussions. The authors also would like to acknowledge Angel
Shi and Charlotte Shi for the proofreading and typo corrections. The editors would like to thank
Guotao Wang of Intel Corp. for his critical review of this Chapter.
References
1. F. Niklaus, G. Stemme, J.-Q. Lu, R. Gutmann, Adhesive wafer bonding. J. Appl. Phys. 99,
031101 (2006)
2. B. Yacobi, S. Martin, K. Davis, A. Hudson, M. Hubert, Adhesive bonding in microelectronics
and photonics. J. Appl. Phys. 91, 6227 (2002)
3. B. Wu, A. Kumar, S. Pamarthy, High aspect ratio silicon etch: a review. J. Appl. Phys. 108,
051101 (2010)
4. J. Gambino, S. Adderly, J. Knickerbocker, An overview of through-silicon-via technology
and manufacturing challenges. Microelectron. Eng. 135, 73–106 (2015)
5. V. Jansen, M.J. de Boer, S. Unnikrishnan, M.C. Louwerse, M.C. Elwenspoek, Black silicon
method X: a review on high speed and selective plasma etching of silicon with profile control:
an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next
generation equipment. J. Micromech. Microeng. 19, 033001 (2009)
6. D. Henry, F. Jacquet, M. Neyret, X. Bailin, T. Enot, V. Lapras, C. Brunet-Manquat, J. Charbonnier, B. Aventurier, N. Sillon, Through silicon vias technology for CMOS image sensor
packaging, in Electronic Components and Technology Conference, pp. 556–562 (2008)
7. M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, Fabrication of 3D
packaging TSV using DRIE, in Design, Test, Integration and Packaging of MEMS/MOEMS
(2008)
8. D. Bai, X. Zhong, R. Puligadda, J. Burggraf, D. Burgstaller, C. Lypka, J. Verzosa, Edge
protection of temporary bonded wafers during backgrinding. ECS Trans. 18, 757–762 (2009)
9. J. Lu, J. Mcmahon, R. Gutmann, 3D integration using adhesive, metal, and metal/adhesive as
wafer bonding interfaces, in MRS Fall Meeting Symposium E, pp. 1112–E02–01 (2008)
10. R. Puligadda, S. Pillalamarri, W. Hong, C. Brubaker, M. Wimplinger, S. Pargfrieder, High
performance temporary adhesive for wafer bonding applications. Mater. Res. Soc. Proc. 970,
0970–Y04–09 (2007)
H. Ma et al.
should be increased while the epoxy weight (M) and epoxy contact angel at substrate
(θ ) should be reduced.
7.10 Conclusions
In summary, we briefly overviewed the general TSV wafer fabrication processes and
dived into the fundamentals and failures of temporary wafer bonding and debonding,
laser scribe, wafer saw dicing, die pick and place, chip attach and underfill processes.
Understanding the temporary wafer bonding and debonding and die preparation
process mechanisms and fundamentals is key to deliver a high yield and reliable
process for 3D packaging.
Acknowledgements The authors would like to acknowledge Dr. Sairam Agraharam and Dr. Jay
Cheng of Intel Corp. for valuable discussions. The authors also would like to acknowledge Angel
Shi and Charlotte Shi for the proofreading and typo corrections. The editors would like to thank
Guotao Wang of Intel Corp. for his critical review of this Chapter.
References
1. F. Niklaus, G. Stemme, J.-Q. Lu, R. Gutmann, Adhesive wafer bonding. J. Appl. Phys. 99,
031101 (2006)
2. B. Yacobi, S. Martin, K. Davis, A. Hudson, M. Hubert, Adhesive bonding in microelectronics
and photonics. J. Appl. Phys. 91, 6227 (2002)
3. B. Wu, A. Kumar, S. Pamarthy, High aspect ratio silicon etch: a review. J. Appl. Phys. 108,
051101 (2010)
4. J. Gambino, S. Adderly, J. Knickerbocker, An overview of through-silicon-via technology
and manufacturing challenges. Microelectron. Eng. 135, 73–106 (2015)
5. V. Jansen, M.J. de Boer, S. Unnikrishnan, M.C. Louwerse, M.C. Elwenspoek, Black silicon
method X: a review on high speed and selective plasma etching of silicon with profile control:
an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next
generation equipment. J. Micromech. Microeng. 19, 033001 (2009)
6. D. Henry, F. Jacquet, M. Neyret, X. Bailin, T. Enot, V. Lapras, C. Brunet-Manquat, J. Charbonnier, B. Aventurier, N. Sillon, Through silicon vias technology for CMOS image sensor
packaging, in Electronic Components and Technology Conference, pp. 556–562 (2008)
7. M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, Fabrication of 3D
packaging TSV using DRIE, in Design, Test, Integration and Packaging of MEMS/MOEMS
(2008)
8. D. Bai, X. Zhong, R. Puligadda, J. Burggraf, D. Burgstaller, C. Lypka, J. Verzosa, Edge
protection of temporary bonded wafers during backgrinding. ECS Trans. 18, 757–762 (2009)
9. J. Lu, J. Mcmahon, R. Gutmann, 3D integration using adhesive, metal, and metal/adhesive as
wafer bonding interfaces, in MRS Fall Meeting Symposium E, pp. 1112–E02–01 (2008)
10. R. Puligadda, S. Pillalamarri, W. Hong, C. Brubaker, M. Wimplinger, S. Pargfrieder, High
performance temporary adhesive for wafer bonding applications. Mater. Res. Soc. Proc. 970,
0970–Y04–09 (2007)