7 Fundamentals and Failures in Die Preparation for 3D Packaging
189
Fig. 7.28 Displacement contour for the IC chip. (Color figure online) [92]
crucial parameters that need to be considered while setting process conditions is the
electrostatic discharge (ESD) as this will severely damage the TSV silicon.
7.8 Chip Attach
Chip attach is used to attach chip to substrate (C2S) or chip to wafer (C2W). In
general, chip attach process flow includes flux jetting (or dipping), chip pick and
place, reflow and cleaning (or deflux). During N 2 reflow process, flux is activated
to remove metal oxide; once reflow temperature reaches solder liquidus temperature, solder melts and wets metal pad. During cleaning process, flux residue will be
removed by water or chemical because flux residue might induce underfill voiding and
pose reliability risk such as underfill delamination, solder joint short, electrochemical
migration or corrosion.
Table 7.1 summarized different flip chip soldering methods. Mass reflow (MR)
and thermal compression bonding (TCB) have been discussed by many research
groups and companies and won’t be repeated here [94–97]. Amkor Technology Inc.
published several papers about the application of Laser Assisted Bonding (LAB)
on chip attach [98, 99]. Junior et al. expanded the application of Laser-Assisted
Bonding to 3D packaging [100]. Similar to MR, the process flow with LAB starts
with flux dipping or jetting. Once chip attachment is completed, LAB process uses
rectangular homogenized Near-Infrared laser beam (such as 980 nm) to heat up
the chip and substrate. The size of laser beam should be relative larger than chip
size. Once laser hits silicon surface, laser reflection and refraction will occur. Based
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