7 Fundamentals and Failures in Die Preparation for 3D Packaging
161
removing the grinding induced damage layer, different types of stress relieving
approaches have been applied to increase the silicon strength, including Chemical
Mechanical Polishing (CMP), dry polishing, wet etch, and dry etch. Both CMP and
dry polishing use polyurethane-based polish pad. CMP also needs slurry, which is
a mixture of abrasive particle, water, and base. Dry etch uses fluorine and oxygen
based plasmas (i.e. CF 4 , SF 6 , O 2 , etc.) to etch silicon. Wet etch uses acid (such as
hydrofluoric, nitric acid, etc.) to etch silicon. If the thickness and mechanical modulus
of temporary bonding adhesive are not optimized and the residual compressive stress
inside FEOL and BEOL is too high, buckling or wrinkling of device wafer might
occur, causing challenges in the downstream processes. The mechanism and solutions
for this issue will be discussed in details in the following.
Once target silicon thickness is achieved, photolithography process is used for
TSV patterning. Because silicon is transparent to infrared (IR) wavelengths, IR
camera is used to detect the metal fiducial marks at Back-End-of-Line through bulk
silicon. Different types of alignment keys have been proposed to improve the overlay
placement resolution [20, 21]. If device wafer has buckling or wrinkling issue, this
TSV patterning process might be challenging. Post TSV patterning, TSV silicon
etch or removal is done by either plasma dry etch or laser drilling [3–5]. Among
various high aspect ratio silicon etching processes, Bosch process is a common
method adopted for TSV silicon etch, which alternates etching (SF 6 ) and passivation
(C 4 F 8 ). By considering the kinetics of plasma radical diffusion, reaction and recombination inside pore, via, and trench, Shi et al. proposed a Plasma Altered Layer
model to investigate the chemical effect of plasma interaction with porous low-k
dielectrics in the low plasma energy region [22, 23]. Based on this Plasma Altered
Layer model, there are more reactions at the outer edge or top surface of pore, via
and trench. Shi et al. also introduced Sputtering Yield model to evaluate the physical effect of plasma interaction with porous low-k dielectrics in the high plasma
energy region [24]. Based on this Sputtering Yield model, the sputtering yield is
proportional to the square root of DC bias voltage and also depends on the material
density and ion incident angle. Similar concepts can be extended to study TSV silicon
etching. One issue related to Bosch process is the TSV sidewall scallop, which caused
challenges in the downstream processes. By using Depth Resolved Photoemission
Microscopy, IR-Optical-Beam-Induced Resistance Change, Lock-In Thermography
(LIT), and Electron Beam Absorbed Current (EBAC), the diode-like TSV leakage
or short issue has been investigated by several groups [25–29]. Transmission Electron Microscopy (TEM) revealed local contact between TSV metal filling and bulk
silicon. By optimizing the TSV etch process, the sidewall roughness was reduced and
TSV leakage failure decreased. Another issue related to Bosch process is the silicon
etching uniformity across wafer. Inductive Coupled Plasma (ICP) is usually used
to generate plasma. However, the intrinsic non-uniformity issue of plasma density
distribution might induce TSV open and short yield loss. If the TSV etching process
is targeting at perfect etching in the center of wafer, there might be remaining silicon
at the edge of wafer, causing TSV open failure there; if the TSV etching process is
targeting at perfect etching at the edge of wafer, there might be over-etching in the
center of wafer, causing TSV leakage or short failure there.
161
removing the grinding induced damage layer, different types of stress relieving
approaches have been applied to increase the silicon strength, including Chemical
Mechanical Polishing (CMP), dry polishing, wet etch, and dry etch. Both CMP and
dry polishing use polyurethane-based polish pad. CMP also needs slurry, which is
a mixture of abrasive particle, water, and base. Dry etch uses fluorine and oxygen
based plasmas (i.e. CF 4 , SF 6 , O 2 , etc.) to etch silicon. Wet etch uses acid (such as
hydrofluoric, nitric acid, etc.) to etch silicon. If the thickness and mechanical modulus
of temporary bonding adhesive are not optimized and the residual compressive stress
inside FEOL and BEOL is too high, buckling or wrinkling of device wafer might
occur, causing challenges in the downstream processes. The mechanism and solutions
for this issue will be discussed in details in the following.
Once target silicon thickness is achieved, photolithography process is used for
TSV patterning. Because silicon is transparent to infrared (IR) wavelengths, IR
camera is used to detect the metal fiducial marks at Back-End-of-Line through bulk
silicon. Different types of alignment keys have been proposed to improve the overlay
placement resolution [20, 21]. If device wafer has buckling or wrinkling issue, this
TSV patterning process might be challenging. Post TSV patterning, TSV silicon
etch or removal is done by either plasma dry etch or laser drilling [3–5]. Among
various high aspect ratio silicon etching processes, Bosch process is a common
method adopted for TSV silicon etch, which alternates etching (SF 6 ) and passivation
(C 4 F 8 ). By considering the kinetics of plasma radical diffusion, reaction and recombination inside pore, via, and trench, Shi et al. proposed a Plasma Altered Layer
model to investigate the chemical effect of plasma interaction with porous low-k
dielectrics in the low plasma energy region [22, 23]. Based on this Plasma Altered
Layer model, there are more reactions at the outer edge or top surface of pore, via
and trench. Shi et al. also introduced Sputtering Yield model to evaluate the physical effect of plasma interaction with porous low-k dielectrics in the high plasma
energy region [24]. Based on this Sputtering Yield model, the sputtering yield is
proportional to the square root of DC bias voltage and also depends on the material
density and ion incident angle. Similar concepts can be extended to study TSV silicon
etching. One issue related to Bosch process is the TSV sidewall scallop, which caused
challenges in the downstream processes. By using Depth Resolved Photoemission
Microscopy, IR-Optical-Beam-Induced Resistance Change, Lock-In Thermography
(LIT), and Electron Beam Absorbed Current (EBAC), the diode-like TSV leakage
or short issue has been investigated by several groups [25–29]. Transmission Electron Microscopy (TEM) revealed local contact between TSV metal filling and bulk
silicon. By optimizing the TSV etch process, the sidewall roughness was reduced and
TSV leakage failure decreased. Another issue related to Bosch process is the silicon
etching uniformity across wafer. Inductive Coupled Plasma (ICP) is usually used
to generate plasma. However, the intrinsic non-uniformity issue of plasma density
distribution might induce TSV open and short yield loss. If the TSV etching process
is targeting at perfect etching in the center of wafer, there might be remaining silicon
at the edge of wafer, causing TSV open failure there; if the TSV etching process is
targeting at perfect etching at the edge of wafer, there might be over-etching in the
center of wafer, causing TSV leakage or short failure there.