RRAM-Based Neuromorphic Computing Systems
385
Fig. 2 Crossbar array of two-terminal synaptic devices in a neuromorphic core, allowing a direct
mapping of the weight values to the algorithm. This figure is adapted from [4]
multilevel conductance characteristics of at least 32 levels (5-bit). However, due to
inherent cycle-to-cycle and device-to-device variation of RRAM devices, trade-off
in the number of bits per cell might be required to accommodate the state variation
allowing sufficient read margin in between the states. Tighter distribution of the
states can be achieved by implementation of write-verify scheme at the expense
of programming energy and overall speed. The more conductance levels obtained
within a single synapse will enhance the network immunity towards input noise, thus
realizing higher learning and test accuracy. Despite that, the number of bits required
per cell is still subjected to the network architecture and algorithms implemented.
Linearity of the weight update is associated with the relationship between the change
of weight value for every programming cycle, while the symmetry is referring to the
change of weight value during potentiation and depression cycle. Symmetric linear
weight update feature will allow convenient direct mapping of the device conductance
and the algorithm weight values. Furthermore, it will enable more efficient training
process through state-independent weight update. However, due to the two-terminal
nature of RRAM devices, asymmetric nonlinear change of conductance is a huge
challenge. This undesired feature has been shown to significantly reduce the network
learning accuracy. Thus, different techniques from materials and circuits perspective
as well as hardware-algorithm co-optimizations have been investigated.
Other requirements from key device performance parameters consist of endurance
characteristics of ≥10
9 , long data retention of ≥10 years, low programming energy
of ≤10 fJ, high scalability of ≤10 nm, and maximum dynamic ratio of ≥100. High
385
Fig. 2 Crossbar array of two-terminal synaptic devices in a neuromorphic core, allowing a direct
mapping of the weight values to the algorithm. This figure is adapted from [4]
multilevel conductance characteristics of at least 32 levels (5-bit). However, due to
inherent cycle-to-cycle and device-to-device variation of RRAM devices, trade-off
in the number of bits per cell might be required to accommodate the state variation
allowing sufficient read margin in between the states. Tighter distribution of the
states can be achieved by implementation of write-verify scheme at the expense
of programming energy and overall speed. The more conductance levels obtained
within a single synapse will enhance the network immunity towards input noise, thus
realizing higher learning and test accuracy. Despite that, the number of bits required
per cell is still subjected to the network architecture and algorithms implemented.
Linearity of the weight update is associated with the relationship between the change
of weight value for every programming cycle, while the symmetry is referring to the
change of weight value during potentiation and depression cycle. Symmetric linear
weight update feature will allow convenient direct mapping of the device conductance
and the algorithm weight values. Furthermore, it will enable more efficient training
process through state-independent weight update. However, due to the two-terminal
nature of RRAM devices, asymmetric nonlinear change of conductance is a huge
challenge. This undesired feature has been shown to significantly reduce the network
learning accuracy. Thus, different techniques from materials and circuits perspective
as well as hardware-algorithm co-optimizations have been investigated.
Other requirements from key device performance parameters consist of endurance
characteristics of ≥10
9 , long data retention of ≥10 years, low programming energy
of ≤10 fJ, high scalability of ≤10 nm, and maximum dynamic ratio of ≥100. High