386
P. A. Dananjaya et al.
endurance capability is required to allow more training cycles for the network. This
is especially important for on-chip learning implementation. On the other hand, long
retention is important to accommodate more inference processes, in which the weight
values are read with minimum read disturbance. If the data retention of the device is
poor, the number of inferences can be done without refreshing the weight value will
be relatively lower. Trade-off between endurance and retention in RRAM devices has
been reported, thus optimization from materials and programming point of view must
be thoroughly considered. In order to not only mimic human brain functionalities
but also its efficiency, the device must be able to operate in the order of ~10 fJ
per synaptic event. This is one of the most challenging aspects in synaptic device
engineering, especially in highly scalable two-terminal devices since programming
and reading of the states are done through the same terminals. This leads to another
trade-off with device retention. A long data retention requires high state energy
barrier to reduce the effect of external disturbance such as heat and electric field,
however at the same time this energy barrier must be sufficiently low to achieve low
programming energy requirement. Like high density storage devices, highly scalable
device footprint is also desired for synaptic device applications to enable large scale
neural network within compact chip dimension. In order to fully utilize the high
scalability of RRAM devices, a two-terminal select device is required to facilitate the
real crossbar array implementation. This can potentially add on to the challenging task
of achieving linear and symmetrical weight update. Dynamic ratio is defined as the
ratio of the highest conductance value to the lowest one. Higher dynamic ratio can be
translated into more superior mapping capability of the network. It also enables larger
network connectivity in which maintaining sufficient read margin is crucial. These
correlations among the device parameters post an enormous challenge in finding a
reliable device that can provide excellent scalability while maintaining high synaptic
performances. Thus, device, circuit, and algorithm-level co-optimization is needed
(Fig. 3).
Fig. 3 Ideal analog synapse
properties with gradual,
linear, and symmetrical
weight modulation under
identical programming pulse
condition with sufficient
margin between the states
and large dynamic ratio
0
4
8
12 16 20 24 28 32
0.0
0.2
0.4
0.6
0.8
1.0
D
e
p
r
e
s
s
i
o
n
Normalized Conductance
#Programming Pulse
P o t e n t i a t i o n
> 100 x
P. A. Dananjaya et al.
endurance capability is required to allow more training cycles for the network. This
is especially important for on-chip learning implementation. On the other hand, long
retention is important to accommodate more inference processes, in which the weight
values are read with minimum read disturbance. If the data retention of the device is
poor, the number of inferences can be done without refreshing the weight value will
be relatively lower. Trade-off between endurance and retention in RRAM devices has
been reported, thus optimization from materials and programming point of view must
be thoroughly considered. In order to not only mimic human brain functionalities
but also its efficiency, the device must be able to operate in the order of ~10 fJ
per synaptic event. This is one of the most challenging aspects in synaptic device
engineering, especially in highly scalable two-terminal devices since programming
and reading of the states are done through the same terminals. This leads to another
trade-off with device retention. A long data retention requires high state energy
barrier to reduce the effect of external disturbance such as heat and electric field,
however at the same time this energy barrier must be sufficiently low to achieve low
programming energy requirement. Like high density storage devices, highly scalable
device footprint is also desired for synaptic device applications to enable large scale
neural network within compact chip dimension. In order to fully utilize the high
scalability of RRAM devices, a two-terminal select device is required to facilitate the
real crossbar array implementation. This can potentially add on to the challenging task
of achieving linear and symmetrical weight update. Dynamic ratio is defined as the
ratio of the highest conductance value to the lowest one. Higher dynamic ratio can be
translated into more superior mapping capability of the network. It also enables larger
network connectivity in which maintaining sufficient read margin is crucial. These
correlations among the device parameters post an enormous challenge in finding a
reliable device that can provide excellent scalability while maintaining high synaptic
performances. Thus, device, circuit, and algorithm-level co-optimization is needed
(Fig. 3).
Fig. 3 Ideal analog synapse
properties with gradual,
linear, and symmetrical
weight modulation under
identical programming pulse
condition with sufficient
margin between the states
and large dynamic ratio
0
4
8
12 16 20 24 28 32
0.0
0.2
0.4
0.6
0.8
1.0
D
e
p
r
e
s
s
i
o
n
Normalized Conductance
#Programming Pulse
P o t e n t i a t i o n
> 100 x