Resistive Random Access Memory Device …
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remain for practical CRS implementation such as the shared inner metal electrode and
the inherent variability of each CBRAM in a CRS cell. It is also difficult to reduce the
operation current in the CRS since the variability increases with the current reduction
[120–122].
Another self-rectifying concept is to have a hybrid RRAM-selector cell such as
the 3D double layer vertical structure demonstrated by Hou et al. [123–125]. By
utilizing a Ta/TaO x /TiO x /Ti MIIM stack, stable bipolar resistive switching with over
10
3 self-rectifying ratio as well as superior endurance over 10
10 cycles for both top and
bottom MIIM cells. Homogeneous interfacial switching mechanism was proposed to
elucidate the bipolar resistive switching mode and self-rectification [124]. The key
merit of this structure is the absence of the additional inner middle electrode that
separates the RRAM from the selector which makes it very attractive for the high
density vertical 3D crosspoint architecture.
In 2017, Luo et al. demonstrated a bit cost scalable, 8-layer vertical 3D RRAM
using a hybrid RRAM-selector cell [126]. With a TiN/HfO 2 /TaO x /Ti MIIM stack,
the devices exhibited >100 non-linearity and high endurance (>10
7 ). In addition,
scalability down to 5 nm device size and 4 nm vertical pitch in a 3D RRAM array
was also demonstrated [126]. Despite its high performance and scalability, the high
LRS and HRS resistances in the G range might require innovative circuit design.
3.2 RRAM Design with Selection Device
Since most RRAM devices operate in the bipolar switching mode, we will focus
on two-terminal selection devices compatible with bipolar RRAM. Based on I-V
characteristics, Yu et al. broadly categorized these selection devices into two groups:
Type I (Exponential I-V selectors) and Type II (Threshold I-V selectors) [127].
Figure 11 shows the typical I-V characteristics of a bipolar RRAM device with
Type I and Type II selectors. The two key selector performance metrics are (1) nonlinearity, which is the current ratio between V w and V w /2, and (2) drive current
density, which ideally has to be higher than 10 MA/cm
2 if the device scales below
the 10 nm technology node. The selector non-linearity ensures limited sneak current
from unselected memory devices during write and read operations. Other selector
performance metrics such as speed, cycling endurance, variability should ideally be
as good as or better than the memory cell that it is paired with. In addition, the selector
material and fabrication process should also be CMOS compatible.
As seen in Fig. 11a, Type I selectors employ an exponential I-V curve to switch
on the selector with a current increase of several orders of magnitude, resulting
in high non-linearity. Reported Type I selectors usually involve engineering the
oxide/electrode interface to form a Schottky barrier [128–130] or MIM structures
with a tunnelling oxide barrier [131–134].
Ideally, Type II selectors are more preferred due to their sudden turn-on property
with steep slope. Type II selectors usually show a hysteresis in their I-V characteristics as depicted in Fig. 11b, where they turn on above a threshold voltage and turns off
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