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M. Becherer
or even current induced switching techniques like Spin-transfer torque (STT) or
Spin-orbit torque (SOT) by electrically accessing each element on device level.
Switching speed: We think, that switching speed (clocking speed) in the MHzregime is not a show-stopper for NML technology, as due to nonvolatility and
high integration density data throughput is competitive with CMOS. However,
CMOS is a circuit implementation, optimized over decades and an emerging
technology has to promise (and at some point has to deliver) improvements of
orders in magnitude to be accepted in an industrial environment.
The given list is far from being comprehensive, and many aspects of NML pros
and cons are not taken into account. But micro-, nanomagnetism and spintronics
are flourishing fields and new effects and novel material are around the corner. The
given pNML platform is ripe to be improved by scientists and engineers: in any case,
pNML 2.0 (if the presented work could be summarized as pNML 1.0) will have to be
faster, lower-energy, more robust and fault-tolerant, thus closer to a real disruptive
pNML BEOL technology for logic circuits. Potentially—by overcoming the given
challenges—it could be well suited for digital but non-charge based beyond CMOS
co-processor architectures.
Acknowledgements There are numerous people who greatly contributed to this work, too many
to name them all personally. I would like to thank the Bachelor and Master students of the TUM
nanomagnetic group, the staff of the former TUM Chair for Technical Electronics, the Researchers
Xueming Yu, Josef Kiermaier, Stephan Breitkreutz-v. Gamm, Irina Eichwald and Grazvidas Žiemys,
and my mentors Gyorgy Csaba, Wolfgang Porod and Doris Schmitt-Landsiedel. Financial support
by the German Research Foundation DFG under Grant SCHM 1478/9-1, CS 62/2-1, SCHM 1478/92 and SCHM 1478/11-1 and the Technical University of Munich—Institute for Advanced Study,
funded by the German Excellence Initiative, is gratefully acknowledged.
References
1. The International Technology Roadmap for Semiconductors (ITRS): Emerging Research
Devices. http://www.itrs2.net (2015) http://www.itrs2.net/itrs-reports.html
2. The International Technology Roadmap for Semiconductors (ITRS) 2.0 Executive Summary.
http://www.itrs2.net/itrs-reports.html
3. M. Koyanagi, T. Fukushima, T. Tanaka, Proc. IEEE 97(1), 49 (2009). https://doi.org/10.1109/
JPROC.2008.2007463
4. P.A.T. adn, X. Gu, R. Alapati, M.S. Bakir, IEEE Trans. Components, Packaging Manuf. Technolo. 6(7), 1007 (2016). https://doi.org/10.1109/TCPMT.2016.2524691
5. T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J.K. Park, S. Yamada, F. Pan, Y. Einaga,
A. Ghalam, T. Tanzawa, J. Guo, T. Ichikawa, E. Yu, S. Tamada, T. Manabe, J. Kishimoto,
Y. Oikawa, Y. Takashima, H. Kuge, M. Morooka, A. Mohammadzadeh, J. Kang, J. Tsai,
E. Sirizotti, E. Lee, L. Vu, Y. Liu, H. Choi, K. Cheon, D. Song, D. Shin, J.H. Yun, M. Piccardi,
K.F. Chan, Y. Luthra, D. Srinivasan, S. Deshmukh, K. Kavalipurapu, D. Nguyen, G. Gallo,
S. Ramprasad, M. Luo, Q. Tang, M. Incarnati, A. Macerola, L. Pilolli, L.D. Santis, M. Rossini,
V. Moschiano, G. Santin, B. Tronca, H. Lee, V. Patel, T. Pekny, A. Yip, N. Prabhu, P. Sule,
T. Bemalkhedkar, K. Upadhyayula, C. Jaramillo, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (2016), pp. 142–144. https://doi.org/10.1109/ISSCC.2016.7417947
M. Becherer
or even current induced switching techniques like Spin-transfer torque (STT) or
Spin-orbit torque (SOT) by electrically accessing each element on device level.
Switching speed: We think, that switching speed (clocking speed) in the MHzregime is not a show-stopper for NML technology, as due to nonvolatility and
high integration density data throughput is competitive with CMOS. However,
CMOS is a circuit implementation, optimized over decades and an emerging
technology has to promise (and at some point has to deliver) improvements of
orders in magnitude to be accepted in an industrial environment.
The given list is far from being comprehensive, and many aspects of NML pros
and cons are not taken into account. But micro-, nanomagnetism and spintronics
are flourishing fields and new effects and novel material are around the corner. The
given pNML platform is ripe to be improved by scientists and engineers: in any case,
pNML 2.0 (if the presented work could be summarized as pNML 1.0) will have to be
faster, lower-energy, more robust and fault-tolerant, thus closer to a real disruptive
pNML BEOL technology for logic circuits. Potentially—by overcoming the given
challenges—it could be well suited for digital but non-charge based beyond CMOS
co-processor architectures.
Acknowledgements There are numerous people who greatly contributed to this work, too many
to name them all personally. I would like to thank the Bachelor and Master students of the TUM
nanomagnetic group, the staff of the former TUM Chair for Technical Electronics, the Researchers
Xueming Yu, Josef Kiermaier, Stephan Breitkreutz-v. Gamm, Irina Eichwald and Grazvidas Žiemys,
and my mentors Gyorgy Csaba, Wolfgang Porod and Doris Schmitt-Landsiedel. Financial support
by the German Research Foundation DFG under Grant SCHM 1478/9-1, CS 62/2-1, SCHM 1478/92 and SCHM 1478/11-1 and the Technical University of Munich—Institute for Advanced Study,
funded by the German Excellence Initiative, is gratefully acknowledged.
References
1. The International Technology Roadmap for Semiconductors (ITRS): Emerging Research
Devices. http://www.itrs2.net (2015) http://www.itrs2.net/itrs-reports.html
2. The International Technology Roadmap for Semiconductors (ITRS) 2.0 Executive Summary.
http://www.itrs2.net/itrs-reports.html
3. M. Koyanagi, T. Fukushima, T. Tanaka, Proc. IEEE 97(1), 49 (2009). https://doi.org/10.1109/
JPROC.2008.2007463
4. P.A.T. adn, X. Gu, R. Alapati, M.S. Bakir, IEEE Trans. Components, Packaging Manuf. Technolo. 6(7), 1007 (2016). https://doi.org/10.1109/TCPMT.2016.2524691
5. T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J.K. Park, S. Yamada, F. Pan, Y. Einaga,
A. Ghalam, T. Tanzawa, J. Guo, T. Ichikawa, E. Yu, S. Tamada, T. Manabe, J. Kishimoto,
Y. Oikawa, Y. Takashima, H. Kuge, M. Morooka, A. Mohammadzadeh, J. Kang, J. Tsai,
E. Sirizotti, E. Lee, L. Vu, Y. Liu, H. Choi, K. Cheon, D. Song, D. Shin, J.H. Yun, M. Piccardi,
K.F. Chan, Y. Luthra, D. Srinivasan, S. Deshmukh, K. Kavalipurapu, D. Nguyen, G. Gallo,
S. Ramprasad, M. Luo, Q. Tang, M. Incarnati, A. Macerola, L. Pilolli, L.D. Santis, M. Rossini,
V. Moschiano, G. Santin, B. Tronca, H. Lee, V. Patel, T. Pekny, A. Yip, N. Prabhu, P. Sule,
T. Bemalkhedkar, K. Upadhyayula, C. Jaramillo, in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (2016), pp. 142–144. https://doi.org/10.1109/ISSCC.2016.7417947