3D Nanomagnetic Logic
291
However, with the given device, it can be calculated, that only a few aJ per NAND
operation are dissipated when operating the inductor at 50 MHz [42]. A first benchmarking against CMOS [84] gives a 35 times power saving potential at comparable
binary throughput for 10 vertically stacked functional layers of NAND (or majority
gate) based circuits in pNML.
6 Conclusion and Outlook
Using the local ion irradiation technique for pNML combined with the 3D geometrical arrangements, directed signal flow and logic operation in monolithically
integrated three dimensional computing systems is experimentally demonstrated. A
complete logic family was developed and is now ready for optimization in terms of
integration density, operational speed and robustness against variations. In contrast
to CMOS microelectronics, pNML does not require signal and supply wiring to each
gate, and it has no leakage currents. Furthermore, pNML is non-volatile, and provides
an easy way for global clocking, preventing the complex wiring needed in CMOS
monolithic integration. Even though, computation in the ferromagnetic domain is
mainly unidentified in the domain of IC design, the presented results may provide a
promising technology for future 3D integrated circuits and systems especially when
implemented in a Co-processor or Systolic architecture. But there are limitations and
shortcomings that have to be addressed in future NML research:
Materials: The investigated Co/Pt bilayer stacks are possibly not the best choice
when it comes to bigger circuits, as switching fields are rather high and domainwall-speed is low. Softer material stacks like Co/Ni or CoFeB are potentially
better suited. Recent work in our group also considers asymmetric films stacks
with DMI for enhanced domain wall speeds [85].
ANC: Even though focused ion beam processing is well suited for lab experiments,
IC fabrication would need a parallel process step as e.g. provided through ionimplanter technologies combined with high resolution hard-mask fabrication on
chip. As ANC is a defect-based method to form nucleation sites, one should also
consider local doping or alloying as gentle alternative for ANC creation.
Distributions: Thermally induced switching field distributions can be overcome
by strong field coupling. But distributions stemming from fabrication and ANC
creation are much more difficult to tackle. It is beneficial, that a global and continuous field clock is fixing the time-scale on which switching occurs (Arrhenius-type
variations of switching fields are the same for all magnets) however, due to grains
and pinning in the so-far used perpendicular media, most complex circuits were
limited to a full adder and few ANCs.
On-chip clock: Experimental demonstration of an on-chip field clock as given in
Fig. 20 is still lacking. But we see no fundamental obstacles, that one could
efficiently generate fast and low-loss clocking fields on chip. Field generated by
currents should be more straight-forward than using e.g. multi-ferroic materials
291
However, with the given device, it can be calculated, that only a few aJ per NAND
operation are dissipated when operating the inductor at 50 MHz [42]. A first benchmarking against CMOS [84] gives a 35 times power saving potential at comparable
binary throughput for 10 vertically stacked functional layers of NAND (or majority
gate) based circuits in pNML.
6 Conclusion and Outlook
Using the local ion irradiation technique for pNML combined with the 3D geometrical arrangements, directed signal flow and logic operation in monolithically
integrated three dimensional computing systems is experimentally demonstrated. A
complete logic family was developed and is now ready for optimization in terms of
integration density, operational speed and robustness against variations. In contrast
to CMOS microelectronics, pNML does not require signal and supply wiring to each
gate, and it has no leakage currents. Furthermore, pNML is non-volatile, and provides
an easy way for global clocking, preventing the complex wiring needed in CMOS
monolithic integration. Even though, computation in the ferromagnetic domain is
mainly unidentified in the domain of IC design, the presented results may provide a
promising technology for future 3D integrated circuits and systems especially when
implemented in a Co-processor or Systolic architecture. But there are limitations and
shortcomings that have to be addressed in future NML research:
Materials: The investigated Co/Pt bilayer stacks are possibly not the best choice
when it comes to bigger circuits, as switching fields are rather high and domainwall-speed is low. Softer material stacks like Co/Ni or CoFeB are potentially
better suited. Recent work in our group also considers asymmetric films stacks
with DMI for enhanced domain wall speeds [85].
ANC: Even though focused ion beam processing is well suited for lab experiments,
IC fabrication would need a parallel process step as e.g. provided through ionimplanter technologies combined with high resolution hard-mask fabrication on
chip. As ANC is a defect-based method to form nucleation sites, one should also
consider local doping or alloying as gentle alternative for ANC creation.
Distributions: Thermally induced switching field distributions can be overcome
by strong field coupling. But distributions stemming from fabrication and ANC
creation are much more difficult to tackle. It is beneficial, that a global and continuous field clock is fixing the time-scale on which switching occurs (Arrhenius-type
variations of switching fields are the same for all magnets) however, due to grains
and pinning in the so-far used perpendicular media, most complex circuits were
limited to a full adder and few ANCs.
On-chip clock: Experimental demonstration of an on-chip field clock as given in
Fig. 20 is still lacking. But we see no fundamental obstacles, that one could
efficiently generate fast and low-loss clocking fields on chip. Field generated by
currents should be more straight-forward than using e.g. multi-ferroic materials