290
M. Becherer
Cladding
~ 1mm
I clock
Clocking zone
40 m
µ
Dielectric
Copper wire
Stacked NML layers
S
N
Signal Crossing
~ 60 nm
~ 60 nm
Signal
routing
Magnetic Via
3D Majority
ANC
Fig. 21 On-chip inductor for clocking: Copper wires in a meander-like layout are sandwiched
between soft-magnetic films. Magnetic fields perpendicular to the NML layer stack are generated.
The pNML system is embedded in a dielectric matrix. Typical clocking zones are 40 µm wide and
1 mm long. Graph adapted and reprinted with permission from [19]
envisioned pNML on-chip inductor will be given in the following. For the inductor
estimated by w = 1 µm, l = 80 µm (40 µm-wide clocking zone) and μ r = 1000,
the simplification in Eqn. 5 holds, as 1 µm 80 µm/1000 = 80 nm. With that, the
magnetic induction field can be calculated with I = 30 mA ( j = 3 × 10
9 A m
−2
for a wire with cross-section area of 10 µm
2 ) to B ≈ μ 0 I /2w = 19mT, which is a
reasonable high value for pNML on-chip clocking circuits.
This on-chip inductor design was proposed in [82] and studied by finite-element
simulations in greater detail in [27, 42]. The main results are briefly summarized
in the following: The investigated on-chip inductor with soft magnetic cladding is
depicted in Fig. 21.
The ferromagnetic inductor is highly planar with Cu wires in a meander geometry,
whereas the pNML system is positioned in the ‘slit’ of the ferromagnetic yoke. The
vertical distance between pNML computing layers is in the 60 nm-range. Hence,
several layers (we estimated 10 layers for the given geometry) of pNML can be
stacked while still be penetrated by a spatially homogeneous magnetic field amplitude over large rectangular clocking zones of ≈ 40 µm × 1 mm. First calculations
for this inductor geometry are based on materials that are discussed in [83] and
predict, that pNML can be clocked with an on-chip inductor of L = 10 nH in the
50 MHz frequency range dissipating only ≈ 3W cm
−2 [27, 42]. But there is plenty
of room for engineering the inductor material and geometry for NML power-clock
operation.
M. Becherer
Cladding
~ 1mm
I clock
Clocking zone
40 m
µ
Dielectric
Copper wire
Stacked NML layers
S
N
Signal Crossing
~ 60 nm
~ 60 nm
Signal
routing
Magnetic Via
3D Majority
ANC
Fig. 21 On-chip inductor for clocking: Copper wires in a meander-like layout are sandwiched
between soft-magnetic films. Magnetic fields perpendicular to the NML layer stack are generated.
The pNML system is embedded in a dielectric matrix. Typical clocking zones are 40 µm wide and
1 mm long. Graph adapted and reprinted with permission from [19]
envisioned pNML on-chip inductor will be given in the following. For the inductor
estimated by w = 1 µm, l = 80 µm (40 µm-wide clocking zone) and μ r = 1000,
the simplification in Eqn. 5 holds, as 1 µm 80 µm/1000 = 80 nm. With that, the
magnetic induction field can be calculated with I = 30 mA ( j = 3 × 10
9 A m
−2
for a wire with cross-section area of 10 µm
2 ) to B ≈ μ 0 I /2w = 19mT, which is a
reasonable high value for pNML on-chip clocking circuits.
This on-chip inductor design was proposed in [82] and studied by finite-element
simulations in greater detail in [27, 42]. The main results are briefly summarized
in the following: The investigated on-chip inductor with soft magnetic cladding is
depicted in Fig. 21.
The ferromagnetic inductor is highly planar with Cu wires in a meander geometry,
whereas the pNML system is positioned in the ‘slit’ of the ferromagnetic yoke. The
vertical distance between pNML computing layers is in the 60 nm-range. Hence,
several layers (we estimated 10 layers for the given geometry) of pNML can be
stacked while still be penetrated by a spatially homogeneous magnetic field amplitude over large rectangular clocking zones of ≈ 40 µm × 1 mm. First calculations
for this inductor geometry are based on materials that are discussed in [83] and
predict, that pNML can be clocked with an on-chip inductor of L = 10 nH in the
50 MHz frequency range dissipating only ≈ 3W cm
−2 [27, 42]. But there is plenty
of room for engineering the inductor material and geometry for NML power-clock
operation.