3D Nanomagnetic Logic
285
of opposite directionality (down-up, up-down) together with a stripe shaped magnet,
a magnetic signal crossing is achieved [70]. With crossing devices in 3D, the layout
of circuits can be very much simplified compared to 2D layouts. In summary, binary
states can be propagated within one clocking pulse (due to ferromagnetic coupling
in perpendicular direction) over several layers of pNML in positive or negative zdirection within one clocking pulse. A similar functionality as provided by electrical
interconnects in CMOS devices providing high flexibility in circuit design.
Another viable device is the so-called soft-magnetic input, where a Permalloy
magnet of ellipsoidal shape is setting (programming) a Co/Pt input magnet [71]. It
is able to transform and at the same time focus or concentrate globally applied inplane fields to out-of-plane fields, acting in a local manner and reprogramming Co/Pt
devices i.e. to switch a M-Gate from NAND to NOR behavior and vice versa during
runtime. Further use of the Permalloy structures is envisioned as field-concentrator
for electrical input wires or as cladding material of those.
The 2D majority gate is transformed to a real 3D gate by positioning one input into
a second pNML plane [72]. The most robust M-gate would use 3 active layers with
maximum coupling-field area, with the drawback of a more demanding fabrication
of three active layers. In principle, the demonstrated 2D 5-input majority gate could
be further optimized for multiple active layers in 3D. With that, robust operation
and a more compact design is achieved. As an example the reader is referred to
a 3D pNML Arithmetic-Logic-Unit (ALU) optimized for compact design in a 3D
implementation [57].
5 A Co-processing Unit as Back-End of Line Technology
for pNML
In this section, the vision of a 3D pNML co-processing unit is discussed including
electrical I/O and the integrated magnetic power clock as power supply for pNML
circuits.
5.1 pNML as a Technology for the BEOL
For a monolithically integrated 3D NML system, the 2D pNML planar circuits are
stacked in the BEOL of a standard CMOS process as sketched in Fig. 18. For pNML,
there is no semiconducting crystalline substrate needed, only a highly planarized and
defect free underlayer for seed layer and magnetic thin film growth is mandatory.
This can be easily implemented in a process that already incorporates magnetic RAM
(MRAM) for non-volatile on-chip memory heavily researched in these days. A coprocessor design is targeted, where the main processor is a general purpose CMOS IC
with electrical to magnetic interfaces (e.g. giant-magneto-resistance (GMR) devices,
285
of opposite directionality (down-up, up-down) together with a stripe shaped magnet,
a magnetic signal crossing is achieved [70]. With crossing devices in 3D, the layout
of circuits can be very much simplified compared to 2D layouts. In summary, binary
states can be propagated within one clocking pulse (due to ferromagnetic coupling
in perpendicular direction) over several layers of pNML in positive or negative zdirection within one clocking pulse. A similar functionality as provided by electrical
interconnects in CMOS devices providing high flexibility in circuit design.
Another viable device is the so-called soft-magnetic input, where a Permalloy
magnet of ellipsoidal shape is setting (programming) a Co/Pt input magnet [71]. It
is able to transform and at the same time focus or concentrate globally applied inplane fields to out-of-plane fields, acting in a local manner and reprogramming Co/Pt
devices i.e. to switch a M-Gate from NAND to NOR behavior and vice versa during
runtime. Further use of the Permalloy structures is envisioned as field-concentrator
for electrical input wires or as cladding material of those.
The 2D majority gate is transformed to a real 3D gate by positioning one input into
a second pNML plane [72]. The most robust M-gate would use 3 active layers with
maximum coupling-field area, with the drawback of a more demanding fabrication
of three active layers. In principle, the demonstrated 2D 5-input majority gate could
be further optimized for multiple active layers in 3D. With that, robust operation
and a more compact design is achieved. As an example the reader is referred to
a 3D pNML Arithmetic-Logic-Unit (ALU) optimized for compact design in a 3D
implementation [57].
5 A Co-processing Unit as Back-End of Line Technology
for pNML
In this section, the vision of a 3D pNML co-processing unit is discussed including
electrical I/O and the integrated magnetic power clock as power supply for pNML
circuits.
5.1 pNML as a Technology for the BEOL
For a monolithically integrated 3D NML system, the 2D pNML planar circuits are
stacked in the BEOL of a standard CMOS process as sketched in Fig. 18. For pNML,
there is no semiconducting crystalline substrate needed, only a highly planarized and
defect free underlayer for seed layer and magnetic thin film growth is mandatory.
This can be easily implemented in a process that already incorporates magnetic RAM
(MRAM) for non-volatile on-chip memory heavily researched in these days. A coprocessor design is targeted, where the main processor is a general purpose CMOS IC
with electrical to magnetic interfaces (e.g. giant-magneto-resistance (GMR) devices,