286
M. Becherer
Fig. 18 The co-processor design of a 3D pNML computing system. On top of a CMOS main
processor chip (front-end-of-line (FEOL)), pNML is fabricated in 3 dimensions in the BEOL. As
the pNML co-processor is power-supplied by a magnetic clocking field, electrical interconnects
are needed for I/O and field-clock generation circuitry (ferromagnetic ‘yoke’ of on-chip-inductor)
only. The co-processing unit in pNML can be tailored for specialized tasks, e.g. pattern-matching,
parallel and massively pipelined data processing. Reprinted with permission from [19]
magnetic-tunnel-junction (MTJ) devices as known from magnetic RAM technology).
Electrical wiring is reduced to a minimum as computation takes place via fieldcoupling and magnetic signals are moved along extended DW conductors.
Further, a clock-field generation circuit for logic operation in the pNML circuits
has to be implemented. The magnetic fields are generated by harmonically driven onchip inductors. A ferromagnetic yoke (on-chip inductor with soft-magnetic cladding)
is exciting and power-supplying the 3D pNML system in the BEOL with an alternating field amplitude. The 3D stacking of functional computing layers (up to 10
or more layers are expected to be a reasonable stacking height) with non-volatile
computing states provides signal crossings and vertical signal flow in an easy way
without need of metallic wiring.
5.2 Electrical I/O
For interfacing the pNML chip with CMOS circuitry, different electrical I/O concepts
have already been investigated.
For electrical input we proposed and demonstrated a current carrying wire close
to the ANC of the input magnet [73]. As the distance of the wire can be chosen to
the tens of nanometer range, small field pulses are sufficient to support switching
of the input (or suppression of switching). Please note, this is different to toggleMRAM, where every storage cell has to be addressed in a cross-bar structure. For
high data-throughput of pNML devices, repetitive pulses on the tens of nanosecond
time-scale have to be generated and synchronized with the applied field-clock for
electrical input. As in pNML not more than several hundreds of electrical inputs are
envisioned, circuit complexity for addressing is not a critical issue. It is worth to
mention that other switching mechanisms for electrical input (e.g. the STT-effect,
M. Becherer
Fig. 18 The co-processor design of a 3D pNML computing system. On top of a CMOS main
processor chip (front-end-of-line (FEOL)), pNML is fabricated in 3 dimensions in the BEOL. As
the pNML co-processor is power-supplied by a magnetic clocking field, electrical interconnects
are needed for I/O and field-clock generation circuitry (ferromagnetic ‘yoke’ of on-chip-inductor)
only. The co-processing unit in pNML can be tailored for specialized tasks, e.g. pattern-matching,
parallel and massively pipelined data processing. Reprinted with permission from [19]
magnetic-tunnel-junction (MTJ) devices as known from magnetic RAM technology).
Electrical wiring is reduced to a minimum as computation takes place via fieldcoupling and magnetic signals are moved along extended DW conductors.
Further, a clock-field generation circuit for logic operation in the pNML circuits
has to be implemented. The magnetic fields are generated by harmonically driven onchip inductors. A ferromagnetic yoke (on-chip inductor with soft-magnetic cladding)
is exciting and power-supplying the 3D pNML system in the BEOL with an alternating field amplitude. The 3D stacking of functional computing layers (up to 10
or more layers are expected to be a reasonable stacking height) with non-volatile
computing states provides signal crossings and vertical signal flow in an easy way
without need of metallic wiring.
5.2 Electrical I/O
For interfacing the pNML chip with CMOS circuitry, different electrical I/O concepts
have already been investigated.
For electrical input we proposed and demonstrated a current carrying wire close
to the ANC of the input magnet [73]. As the distance of the wire can be chosen to
the tens of nanometer range, small field pulses are sufficient to support switching
of the input (or suppression of switching). Please note, this is different to toggleMRAM, where every storage cell has to be addressed in a cross-bar structure. For
high data-throughput of pNML devices, repetitive pulses on the tens of nanosecond
time-scale have to be generated and synchronized with the applied field-clock for
electrical input. As in pNML not more than several hundreds of electrical inputs are
envisioned, circuit complexity for addressing is not a critical issue. It is worth to
mention that other switching mechanisms for electrical input (e.g. the STT-effect,