260
M. Becherer
The current key enabling technology for 3D integration are thinned wafers, stacked
and connected with through-silicon vias [3, 4].
To give an example for 3D integration, NAND Flash technology for nonvolatile
memory has already been economically successful [5, 6]. This is mainly due to
the fact that fault tolerances for memory are less critical and memories are highly
regular structures easier to integrate in a 3D manner by stacking dies [2]. However,
true monolithic 3D integration is still in its beginnings especially for logic ICs and
reasons for that are i.e. the very low acceptable error rates, non-regular layouts and
GHz clocking frequencies. Easily speaking, logic ICs are far more demanding and
for monolithic device integration, process technologies with reduced thermal budget
and at the same time high quality conducting, semiconducting and insulating films
are needed. Furthermore, interconnects of different length scales are a must: from
very small, to medium and to very long distances and at the same time, they have to be
provided in a strictly hierarchical manner. To be precise, through silicon vias are not
an option for monolithic integration, as they connect dies only on a long range manner.
It is worthwhile to mention that planar fabrication technology is not contradictory to
3D integration and by overcoming the wiring problem, namely electrical connection
to every single switching element, it would tremendously reduce complexity of the
fabrication technology.
There is a broad spectrum of assessment going on for logic devices that are discussed as beyond CMOS candidates. Following the Taxonomy of ITRS as reviewed
and summarized in [7] there are
• Conventional CMOS FETS,
• Alternate Channel Materials and Structures,
• Charge-Based Devices Beyond Conventional FETs and
• Devices Using Information Carriers other than Electronic Charge,
whereas the latter class of devices with—Information Carriers other than Electronic
Charge, are
• All-spin logic,
• Bilayer Pseudospin FET,
• Excitonic FET,
• Nanomagnetic Logic,
• Spin torque majority gate and
• Spine Wave devices.
The concept of perpendicular Nanomagnetic Logic (pNML) for digital computation—
mainly developed at Technische Universität München and Notre Dame University—
is a subclass of Nanomagnetic Logic, where multilayer stacks are utilized, showing a
ferromagnetic magnetization perpendicular to the film plane. The pNML technology
avoids electronic switches for computation by using ferromagnetic bistable entities,
coupled by magnetic fields. We claim that it is highly beneficial to use such nonvolatile computational states and combine logic functionality with inherent memory
M. Becherer
The current key enabling technology for 3D integration are thinned wafers, stacked
and connected with through-silicon vias [3, 4].
To give an example for 3D integration, NAND Flash technology for nonvolatile
memory has already been economically successful [5, 6]. This is mainly due to
the fact that fault tolerances for memory are less critical and memories are highly
regular structures easier to integrate in a 3D manner by stacking dies [2]. However,
true monolithic 3D integration is still in its beginnings especially for logic ICs and
reasons for that are i.e. the very low acceptable error rates, non-regular layouts and
GHz clocking frequencies. Easily speaking, logic ICs are far more demanding and
for monolithic device integration, process technologies with reduced thermal budget
and at the same time high quality conducting, semiconducting and insulating films
are needed. Furthermore, interconnects of different length scales are a must: from
very small, to medium and to very long distances and at the same time, they have to be
provided in a strictly hierarchical manner. To be precise, through silicon vias are not
an option for monolithic integration, as they connect dies only on a long range manner.
It is worthwhile to mention that planar fabrication technology is not contradictory to
3D integration and by overcoming the wiring problem, namely electrical connection
to every single switching element, it would tremendously reduce complexity of the
fabrication technology.
There is a broad spectrum of assessment going on for logic devices that are discussed as beyond CMOS candidates. Following the Taxonomy of ITRS as reviewed
and summarized in [7] there are
• Conventional CMOS FETS,
• Alternate Channel Materials and Structures,
• Charge-Based Devices Beyond Conventional FETs and
• Devices Using Information Carriers other than Electronic Charge,
whereas the latter class of devices with—Information Carriers other than Electronic
Charge, are
• All-spin logic,
• Bilayer Pseudospin FET,
• Excitonic FET,
• Nanomagnetic Logic,
• Spin torque majority gate and
• Spine Wave devices.
The concept of perpendicular Nanomagnetic Logic (pNML) for digital computation—
mainly developed at Technische Universität München and Notre Dame University—
is a subclass of Nanomagnetic Logic, where multilayer stacks are utilized, showing a
ferromagnetic magnetization perpendicular to the film plane. The pNML technology
avoids electronic switches for computation by using ferromagnetic bistable entities,
coupled by magnetic fields. We claim that it is highly beneficial to use such nonvolatile computational states and combine logic functionality with inherent memory