3D Nanomagnetic Logic
Markus Becherer
Abstract Digital computation by magnetic ordering? That sounds useless or crazy
having powerful CMOS technologies available everywhere at low cost. However,
if it comes to massively parallel and pipelined digital operations with stringent
power constraints, 3D Nanomagnetic Logic might pay off. This chapter gives an
insight on an experimentally demonstrated complete set of logic devices, where the
entities are not electrically connected but fully powered and operated by magnetic
clocking fields. The computing elements are comprised of ferromagnetic islands of
sub-micrometer size, whereas the binary “0” and “1” is encoded in magnetic northand south-pole. This is accomplished by ferromagnetic thin-film materials that show
magnetic anisotropy perpendicular to the plane of the chip. The anisotropy is locally
reduced by focused Ga
+ ion radiation in order to program computation functionality into close-by magnetic islands. Digital signals are propagated by field-driven
domain-walls in lateral direction and via field coupling in vertical direction, enabling
monolithic 3D integration. Based on majority votes that can be re-programmed to
the universal NAND or NOR function, a hybrid co-processor integrated in the backend-of-line CMOS technology is envisioned. Still far from being ready for mass
fabrication, but containing all basic elements for 3D integrated computation with
nonvolatile magnetic states.
1 Introduction to the Concept of pNML
In order to pursue the ongoing scaling of CMOS circuits, beyond CMOS devices
are heavily researched [1]. At the same time, it is a well known fact, that planar
technology having been a story of great success for Integrated Circuits (ICs) over
the last 50 years, will face a limit, latest when approaching atomistic length-scales.
However, in order to pursue the path of the ITRS roadmap—namely increasing device
density by an exponential law—there is a strong trend towards 3D integration [2].
M. Becherer (B)
Chair of Nanoelectronics, Technical University of Munich, Theresienstraße 90, 80333 Munich,
Germany
e-mail: markus.becherer@tum.de
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_8
259
Markus Becherer
Abstract Digital computation by magnetic ordering? That sounds useless or crazy
having powerful CMOS technologies available everywhere at low cost. However,
if it comes to massively parallel and pipelined digital operations with stringent
power constraints, 3D Nanomagnetic Logic might pay off. This chapter gives an
insight on an experimentally demonstrated complete set of logic devices, where the
entities are not electrically connected but fully powered and operated by magnetic
clocking fields. The computing elements are comprised of ferromagnetic islands of
sub-micrometer size, whereas the binary “0” and “1” is encoded in magnetic northand south-pole. This is accomplished by ferromagnetic thin-film materials that show
magnetic anisotropy perpendicular to the plane of the chip. The anisotropy is locally
reduced by focused Ga
+ ion radiation in order to program computation functionality into close-by magnetic islands. Digital signals are propagated by field-driven
domain-walls in lateral direction and via field coupling in vertical direction, enabling
monolithic 3D integration. Based on majority votes that can be re-programmed to
the universal NAND or NOR function, a hybrid co-processor integrated in the backend-of-line CMOS technology is envisioned. Still far from being ready for mass
fabrication, but containing all basic elements for 3D integrated computation with
nonvolatile magnetic states.
1 Introduction to the Concept of pNML
In order to pursue the ongoing scaling of CMOS circuits, beyond CMOS devices
are heavily researched [1]. At the same time, it is a well known fact, that planar
technology having been a story of great success for Integrated Circuits (ICs) over
the last 50 years, will face a limit, latest when approaching atomistic length-scales.
However, in order to pursue the path of the ITRS roadmap—namely increasing device
density by an exponential law—there is a strong trend towards 3D integration [2].
M. Becherer (B)
Chair of Nanoelectronics, Technical University of Munich, Theresienstraße 90, 80333 Munich,
Germany
e-mail: markus.becherer@tum.de
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021
W. S. Lew et al. (eds.), Emerging Non-volatile Memory Technologies,
https://doi.org/10.1007/978-981-15-6912-8_8
259