216
T. T.-H. Kim
Fig. 13 Comparison of
a typical STT and
b field-assisted STT
Magnetization
Vector
Current induced
torque
Damping torque
(a)
Magnetization
Vector
Current induced
torque
Damping torque
Magnetic field
torque
(b)
(Comp.0), subsequently resetting SW to cut the current path. The VEW circuit needs
to be implemented in each bit line, which is different from the VOW scheme. The
VEW scheme is more efficient in saving write power at the cost of area overhead. In
general, the VEW scheme provides more energy saving when the magnetic memory
requires longer write time. If the write pulse is short, the energy saving can be easily
nullified by the energy overhead from the VEW circuit itself. The self-time write
operation in [7] is conceptually similar to the VOW and VEW schemes since it also
detects write completion on the fly and immediately turns off current paths for energy
saving.
Another write technique for magnetic memory is field assisted writing where
additional magnetic field is applied to MTJ devices for easier switching with a larger
spin-transfer torque [8]. Figure 13 depicts the switching concepts of the typical spintorque transfer (STT) and the field-assisted STT. The additional magnetic field torque
destabilizes the MTJ polarity toward the short axis, which reduces the switching
latency [8]. Figure 14 shows the structure of the field-assisted STT MRAM cell.
Similar works are also reported in [9–11]. In [9], an assisting magnetic field is utilized
to set the MTJ devices to an initial reset state before writing operation. However, since
each write operation requires to switch to a reset state, the write latency is doubled.
In [10, 11], several structures and topologies of the field-assisted STT MRAM cells
are described.
Write power reduction techniques are highly demanded since magnetic memory
consumes much more power than other storage-based memories like SRAMs and
DRAMs. One method of reducing power consumption is to selectively write data
after reading and comparing [12]. If the read data is identical to the write data, no
write operation is necessary. However, this scheme requires multiple cycles for write
operation, which is not suitable for high performance.
T. T.-H. Kim
Fig. 13 Comparison of
a typical STT and
b field-assisted STT
Magnetization
Vector
Current induced
torque
Damping torque
(a)
Magnetization
Vector
Current induced
torque
Damping torque
Magnetic field
torque
(b)
(Comp.0), subsequently resetting SW to cut the current path. The VEW circuit needs
to be implemented in each bit line, which is different from the VOW scheme. The
VEW scheme is more efficient in saving write power at the cost of area overhead. In
general, the VEW scheme provides more energy saving when the magnetic memory
requires longer write time. If the write pulse is short, the energy saving can be easily
nullified by the energy overhead from the VEW circuit itself. The self-time write
operation in [7] is conceptually similar to the VOW and VEW schemes since it also
detects write completion on the fly and immediately turns off current paths for energy
saving.
Another write technique for magnetic memory is field assisted writing where
additional magnetic field is applied to MTJ devices for easier switching with a larger
spin-transfer torque [8]. Figure 13 depicts the switching concepts of the typical spintorque transfer (STT) and the field-assisted STT. The additional magnetic field torque
destabilizes the MTJ polarity toward the short axis, which reduces the switching
latency [8]. Figure 14 shows the structure of the field-assisted STT MRAM cell.
Similar works are also reported in [9–11]. In [9], an assisting magnetic field is utilized
to set the MTJ devices to an initial reset state before writing operation. However, since
each write operation requires to switch to a reset state, the write latency is doubled.
In [10, 11], several structures and topologies of the field-assisted STT MRAM cells
are described.
Write power reduction techniques are highly demanded since magnetic memory
consumes much more power than other storage-based memories like SRAMs and
DRAMs. One method of reducing power consumption is to selectively write data
after reading and comparing [12]. If the read data is identical to the write data, no
write operation is necessary. However, this scheme requires multiple cycles for write
operation, which is not suitable for high performance.