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Process-Induced Stress Engineering in CMOS Technology
To fabricate a TSV of size 5μm assuming a practical aspect ratio of 10:1, the
maximum die thickness will be 50 μm. A TSV is a metallic, usually copper
(Cu), wire extending throughout the substrate and insulated by a dielectric
material. The stress magnitude is sensitive to TSV geometry structure; when
the radius of TSV metal increases, more stress is introduced and becomes
saturated. This property makes it sensitive to the layout pattern. Moreover,
during the process, due to the mismatch of coefficients of thermal expansion
between copper and silicon, thermal stresses are observed at the interface
between TSV and silicon substrate, impacting device performance of neighbouring transistors.
Stacking multiple dies to form 3D integrated circuits has emerged as a
promising technology to reduce interconnects delay and power, to increase
device density, and to achieve heterogeneous integration. Through-silicon
vias and metallic wires that connect different dies are a key enabling technology for 3D ICs. Three-dimensional IC technology not only is capable of
increased device density, but also offers heterogeneous integration of dies
from disparate technologies (analogue, digital, mixed signals, sensors,
antennae, and power storage) and from different technology nodes.
As TSVs create thermal stress in the substrate, stress impacts the performance of neighbouring devices. The profile of TSV-induced thermal stress in
silicon follows a distribution similar to that of the leading-edge strain technology [18]. Analysis tools to quantify the impact of thermal stress on device
performance and techniques to reduce this impact are required. Both TSVinduced noise and TSV-induced stress dictate the size of the keep-out zone
for devices. Analyses of the two phenomena need to be performed to create
new design rules for devices in 3D ICs. Thermal management is a challenge
in 3D ICs. TSVs are proposed to extract heat from dies away from the heat
spreader. Detailed analyses that consider dielectric liner and practical TSV
placement are needed. Coupled analyses of thermal and power TSVs are
required to estimate the effective substrate area dedicated to devices.
The effect of elastic anisotropy on the thermal stress distribution in Si is
investigated [19]. The distribution of thermal stresses on the (001) Si wafer
surface is simulated using finite element analysis (FEA). The thermal stresses
on the (001) Si wafer surface are extracted from the simulation results, and
the distributions of normal stresses σ xx are plotted in Figure 3.14(a) and (b),
with the x axis aligned with the [100] and [110] crystal directions, respectively. In the latter, the simulation is performed on the same model, except
with isotropic Si, and the distribution of σ xx on such an isotropic Si wafer surface is shown in Figure 3.14(c). For the sake of comparison, the stress scales in
Figure 3.14(a) to (c) are normalised.
Raman characterisation of TSV-induced stress in Si has been performed
[20]. Figure 3.15a displays a map of the Si Raman peak shift surrounding
a 5 μm square Cu TSV. Positive Raman shifts (green, yellow, red), which
represent compressive stresses, are observed within ~2 μm of the Cu TSV.
Negative Raman shifts (blue), representing tensile stresses, are observed
Process-Induced Stress Engineering in CMOS Technology
To fabricate a TSV of size 5μm assuming a practical aspect ratio of 10:1, the
maximum die thickness will be 50 μm. A TSV is a metallic, usually copper
(Cu), wire extending throughout the substrate and insulated by a dielectric
material. The stress magnitude is sensitive to TSV geometry structure; when
the radius of TSV metal increases, more stress is introduced and becomes
saturated. This property makes it sensitive to the layout pattern. Moreover,
during the process, due to the mismatch of coefficients of thermal expansion
between copper and silicon, thermal stresses are observed at the interface
between TSV and silicon substrate, impacting device performance of neighbouring transistors.
Stacking multiple dies to form 3D integrated circuits has emerged as a
promising technology to reduce interconnects delay and power, to increase
device density, and to achieve heterogeneous integration. Through-silicon
vias and metallic wires that connect different dies are a key enabling technology for 3D ICs. Three-dimensional IC technology not only is capable of
increased device density, but also offers heterogeneous integration of dies
from disparate technologies (analogue, digital, mixed signals, sensors,
antennae, and power storage) and from different technology nodes.
As TSVs create thermal stress in the substrate, stress impacts the performance of neighbouring devices. The profile of TSV-induced thermal stress in
silicon follows a distribution similar to that of the leading-edge strain technology [18]. Analysis tools to quantify the impact of thermal stress on device
performance and techniques to reduce this impact are required. Both TSVinduced noise and TSV-induced stress dictate the size of the keep-out zone
for devices. Analyses of the two phenomena need to be performed to create
new design rules for devices in 3D ICs. Thermal management is a challenge
in 3D ICs. TSVs are proposed to extract heat from dies away from the heat
spreader. Detailed analyses that consider dielectric liner and practical TSV
placement are needed. Coupled analyses of thermal and power TSVs are
required to estimate the effective substrate area dedicated to devices.
The effect of elastic anisotropy on the thermal stress distribution in Si is
investigated [19]. The distribution of thermal stresses on the (001) Si wafer
surface is simulated using finite element analysis (FEA). The thermal stresses
on the (001) Si wafer surface are extracted from the simulation results, and
the distributions of normal stresses σ xx are plotted in Figure 3.14(a) and (b),
with the x axis aligned with the [100] and [110] crystal directions, respectively. In the latter, the simulation is performed on the same model, except
with isotropic Si, and the distribution of σ xx on such an isotropic Si wafer surface is shown in Figure 3.14(c). For the sake of comparison, the stress scales in
Figure 3.14(a) to (c) are normalised.
Raman characterisation of TSV-induced stress in Si has been performed
[20]. Figure 3.15a displays a map of the Si Raman peak shift surrounding
a 5 μm square Cu TSV. Positive Raman shifts (green, yellow, red), which
represent compressive stresses, are observed within ~2 μm of the Cu TSV.
Negative Raman shifts (blue), representing tensile stresses, are observed