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Process-Induced Stress Engineering in CMOS Technology
stresses may be deleterious due to undesirable, nonuniform device performance variations. The introduction of mechanical stress in Si-based integrated circuits, whether desired or undesired, is intrinsic to IC fabrication.
Stress can affect carrier mobility, either negatively or positively, depending
on direction and magnitude of stress and the majority carrier type.
Although strain engineering in the channel region of a MOSFET is beneficial, in 3D architectures, the integration of Cu TSVs through the active region
can induce thermomechanical residual stresses in the nearby Si, which could
lead to undesirable performance variations. It is important to analyse parametric variations caused by proximity effects, such as the impact of layout
on transistor stress state. Localised stress characterisation for FEOL applications commonly uses Raman spectroscopy, an all-optical technique that
is applicable for measuring stress in Si based on changes in the crystalline
vibrational modes. Residual stress measurements in Si are conducted using
micro-Raman spectroscopy.
The thermal stress results in additional process variation and reliability
issues. The management and control of this parasitic stress is important for
3D IC development. It is necessary to investigate and characterise the origins
and levels of the induced stresses. The basic structure of TSV is composed of
two components: conducting metals in the via and the barrier layer around
metal. Copper is one of the materials frequently used to serve as an interconnect between devices due to its better immunity of electron migration
(EM) and lower resistivity. The most prevalent metal used for TSVs is Cu.
This choice is intuitive, considering its high conductivity, compatibility with
current CMOS technology and processing, and the technological expertise
developed since its introduction as the metal interconnect of choice in ICs.
However, due to the large via sizes (currently 5 × 50 μm), there is the problem
of thermally induced stresses in nearby active layer devices due to the large
coefficient of thermal expansion (CTE) mismatch between Cu and Si. Thermal
cycling during the manufacturing process, with temperatures reaching up to
400°C or higher, induces thermomechanical stresses in the nearby Si, which
can affect mobility of nearby devices. This would lead to nonuniform device
performance, which would be a function of distance from Cu TSVs.
Processes in fabricating TSVs include through-wafer via formation, deep
reactive ion etching (DRIE), via filling by deposition of diffusion barrier and
adhesion layers, metallisation, wafer thinning and alignment, and bonding.
Manufacturing constraints associated with TSV etch and via filling processes
dictate TSV size. TSV integration schemes are categorised into via-first (via
formation before CMOS process), via-last (via formation after BEOL), and
via-middle (via between CMOS and BEOL). During TSV fabrication, thermal stress is observed at the interface between TSV and silicon due to the
mismatch in coefficients of thermal expansion between silicon substrate and
metal, where copper is usually adopted as the conducting via.
Since TSV is developed based on metal-insulator-semiconductor (MIS) structure, the parasitic capacitance is different from the traditional interconnect
Process-Induced Stress Engineering in CMOS Technology
stresses may be deleterious due to undesirable, nonuniform device performance variations. The introduction of mechanical stress in Si-based integrated circuits, whether desired or undesired, is intrinsic to IC fabrication.
Stress can affect carrier mobility, either negatively or positively, depending
on direction and magnitude of stress and the majority carrier type.
Although strain engineering in the channel region of a MOSFET is beneficial, in 3D architectures, the integration of Cu TSVs through the active region
can induce thermomechanical residual stresses in the nearby Si, which could
lead to undesirable performance variations. It is important to analyse parametric variations caused by proximity effects, such as the impact of layout
on transistor stress state. Localised stress characterisation for FEOL applications commonly uses Raman spectroscopy, an all-optical technique that
is applicable for measuring stress in Si based on changes in the crystalline
vibrational modes. Residual stress measurements in Si are conducted using
micro-Raman spectroscopy.
The thermal stress results in additional process variation and reliability
issues. The management and control of this parasitic stress is important for
3D IC development. It is necessary to investigate and characterise the origins
and levels of the induced stresses. The basic structure of TSV is composed of
two components: conducting metals in the via and the barrier layer around
metal. Copper is one of the materials frequently used to serve as an interconnect between devices due to its better immunity of electron migration
(EM) and lower resistivity. The most prevalent metal used for TSVs is Cu.
This choice is intuitive, considering its high conductivity, compatibility with
current CMOS technology and processing, and the technological expertise
developed since its introduction as the metal interconnect of choice in ICs.
However, due to the large via sizes (currently 5 × 50 μm), there is the problem
of thermally induced stresses in nearby active layer devices due to the large
coefficient of thermal expansion (CTE) mismatch between Cu and Si. Thermal
cycling during the manufacturing process, with temperatures reaching up to
400°C or higher, induces thermomechanical stresses in the nearby Si, which
can affect mobility of nearby devices. This would lead to nonuniform device
performance, which would be a function of distance from Cu TSVs.
Processes in fabricating TSVs include through-wafer via formation, deep
reactive ion etching (DRIE), via filling by deposition of diffusion barrier and
adhesion layers, metallisation, wafer thinning and alignment, and bonding.
Manufacturing constraints associated with TSV etch and via filling processes
dictate TSV size. TSV integration schemes are categorised into via-first (via
formation before CMOS process), via-last (via formation after BEOL), and
via-middle (via between CMOS and BEOL). During TSV fabrication, thermal stress is observed at the interface between TSV and silicon due to the
mismatch in coefficients of thermal expansion between silicon substrate and
metal, where copper is usually adopted as the conducting via.
Since TSV is developed based on metal-insulator-semiconductor (MIS) structure, the parasitic capacitance is different from the traditional interconnect