72
Strain-Engineered MOSFETs
concern. As BEOL processing involves large amounts of stress, stress becomes
a primary issue for BEOL reliability with low-k dielectrics, which are more
fragile. The main BEOL reliability concerns with copper interconnects and
low-k dielectrics are stress migration, time-dependent dielectric breakdown
(TDDB) or bias temperature stability (BTS), delamination and crack formations, copper diffusion into low-k, and electromigration. Electromigration is
mainly a result of electrical stress, but it can also get worse due to mechanical
stress gradients. It has been indicated that electromigration can be impacted
by mechanical stress, particularly in the interconnect extensions close to vias.
Beyond mechanical stress, concerns also include thermal and electrical stress.
As continued scaling becomes increasingly difficult, 3D integration has
emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-silicon via (TSV), which directly connects stacked structures die to die, is one of the key techniques enabling 3D integration [11]. The
advent of 3D integrated circuit (ICs) also provides the opportunity for the
on-chip integration of heterogeneous devices and technologies such as memory, logic, radio frequency (RF), and sensing circuits. Multiple techniques
exist to achieve 3D stacking, including wire bonding, monolithic integration,
and TSVs. TSVs can be used for routing signals, power delivery, and heat
extraction.
Through-silicon via is a promising and key technology to integrate chips
with diverse functionalities by stacking chips vertically for implementation
of 3D ICs with less space and better performance. TSVs can be used to route
interdie signals, deliver power to each die, and extract heat from the dies farther away from the heat sink. Three-dimensional ICs have short interconnects
among each function block, leading to better RC delay. The most important
advantage of TSV structures is that the vertical interconnect successfully
addresses the 2D interconnect problem by replacing long horizontal interconnects with short vertical interconnects. As a result, the RC delay, cross talk, and
power dissipation will be greatly improved. However, the TSV impact on transistor performance is usually not known until the TSV process is stable and
commercialised. Unlike the state-of-the-art strain technologies, such as e-SiGe
or DSL, TSV thermal stress is not an intentional technique applied to improve
device performance. TSV-induced stresses can lead to such effects as delamination, void formation and migration, and fracture, and can significantly affect
device performance. TSV-induced substrate noise increases leakage current,
which increases static power consumption. As a result, stress development is a
major concern for reliability, process control, and device design.
Stress development in ICs can occur at any stage of the manufacturing process from a variety of sources. Two critical areas of Si stress development in
ICs are those that can affect MOSFET performance: (1) front-end-of-the-line
(FEOL) strain-engineered Si channel for increasing carrier mobility and (2)
thermomechanical stress development near Cu TSVs for 3D integration. In
both cases, stresses that develop in Si affect device performance; however, in
the first case, these stresses are desirable, whereas in the second case, these
Strain-Engineered MOSFETs
concern. As BEOL processing involves large amounts of stress, stress becomes
a primary issue for BEOL reliability with low-k dielectrics, which are more
fragile. The main BEOL reliability concerns with copper interconnects and
low-k dielectrics are stress migration, time-dependent dielectric breakdown
(TDDB) or bias temperature stability (BTS), delamination and crack formations, copper diffusion into low-k, and electromigration. Electromigration is
mainly a result of electrical stress, but it can also get worse due to mechanical
stress gradients. It has been indicated that electromigration can be impacted
by mechanical stress, particularly in the interconnect extensions close to vias.
Beyond mechanical stress, concerns also include thermal and electrical stress.
As continued scaling becomes increasingly difficult, 3D integration has
emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-silicon via (TSV), which directly connects stacked structures die to die, is one of the key techniques enabling 3D integration [11]. The
advent of 3D integrated circuit (ICs) also provides the opportunity for the
on-chip integration of heterogeneous devices and technologies such as memory, logic, radio frequency (RF), and sensing circuits. Multiple techniques
exist to achieve 3D stacking, including wire bonding, monolithic integration,
and TSVs. TSVs can be used for routing signals, power delivery, and heat
extraction.
Through-silicon via is a promising and key technology to integrate chips
with diverse functionalities by stacking chips vertically for implementation
of 3D ICs with less space and better performance. TSVs can be used to route
interdie signals, deliver power to each die, and extract heat from the dies farther away from the heat sink. Three-dimensional ICs have short interconnects
among each function block, leading to better RC delay. The most important
advantage of TSV structures is that the vertical interconnect successfully
addresses the 2D interconnect problem by replacing long horizontal interconnects with short vertical interconnects. As a result, the RC delay, cross talk, and
power dissipation will be greatly improved. However, the TSV impact on transistor performance is usually not known until the TSV process is stable and
commercialised. Unlike the state-of-the-art strain technologies, such as e-SiGe
or DSL, TSV thermal stress is not an intentional technique applied to improve
device performance. TSV-induced stresses can lead to such effects as delamination, void formation and migration, and fracture, and can significantly affect
device performance. TSV-induced substrate noise increases leakage current,
which increases static power consumption. As a result, stress development is a
major concern for reliability, process control, and device design.
Stress development in ICs can occur at any stage of the manufacturing process from a variety of sources. Two critical areas of Si stress development in
ICs are those that can affect MOSFET performance: (1) front-end-of-the-line
(FEOL) strain-engineered Si channel for increasing carrier mobility and (2)
thermomechanical stress development near Cu TSVs for 3D integration. In
both cases, stresses that develop in Si affect device performance; however, in
the first case, these stresses are desirable, whereas in the second case, these