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Process-Induced Stress Engineering in CMOS Technology
from the 90 nm node, companies such as IBM, Intel, Texas Instruments, and
Freescale have incorporated the selective epitaxial growth technique to transfer uniaxial compressive stress into the Si channel by growing a local epitaxial
film of SiGe in the source and drain regions of p-MOSFETs. Depending on the
proximity of the SiGe to the channel and the Ge content, 500–900 MPa stress
is created in the channel. Using this technique, impressive saturation drain
current enhancement up to 20–25% has been demonstrated for p-MOSFETs.
A tensile Si nitride capping layer is used to introduce tensile uniaxial strain
into the n-MOSFET, which enhanced the drive current by 10%.
Uniaxial strain is superior to biaxial strain in the following aspects:
1. Uniaxial stress can offer high hole mobility enhancement in both
low strain and high vertical electric fields due to additive strain and
confined splitting, larger two-dimensional in-plane density of states,
and smaller conductivity mass.
2. Uniaxial stress-enhanced electron and hole mobilities mainly arise
from reduced conductivity effective mass vs. reduced scattering for
biaxial stress. Therefore, uniaxial stress provides larger drive current improvement for nanoscale short-channel devices with minimal increases in manufacturing complexity.
3. Uniaxial stress causes n-channel threshold voltage shifts that are
approximately five times smaller, and thus do not require adjustment in substrate doping.
4. Process-induced uniaxial stress increases with decreasing channel length.
5. A uniaxially strained device shows much better reliability.
6. Smaller leakages arise from reduced band gap narrowing, compared
with biaxial tensile stress, which causes much greater band-to-band
tunneling (BTBT) leakage.
7. Significantly less strain is required for hole mobility enhancement
when applying longitudinal uniaxial compression vs. in-plane biaxial tension using the conventional SiGe substrate approach. Therefore,
process-induced uniaxial stress is very promising for scaling down
CMOS technology per the goals of the proposed road map.
3.9 BEOL Stress: Through-Silicon Via
Stress has an impact on all of these reliability concerns. Back-end-of-the-line
(BEOL) stress is very important in terms of interconnect and dielectric reliability. Going toward the 32 nm node, a key challenge is BEOL integration.
In particular, dielectric reliability in the regime of low-k dielectrics is a major
Process-Induced Stress Engineering in CMOS Technology
from the 90 nm node, companies such as IBM, Intel, Texas Instruments, and
Freescale have incorporated the selective epitaxial growth technique to transfer uniaxial compressive stress into the Si channel by growing a local epitaxial
film of SiGe in the source and drain regions of p-MOSFETs. Depending on the
proximity of the SiGe to the channel and the Ge content, 500–900 MPa stress
is created in the channel. Using this technique, impressive saturation drain
current enhancement up to 20–25% has been demonstrated for p-MOSFETs.
A tensile Si nitride capping layer is used to introduce tensile uniaxial strain
into the n-MOSFET, which enhanced the drive current by 10%.
Uniaxial strain is superior to biaxial strain in the following aspects:
1. Uniaxial stress can offer high hole mobility enhancement in both
low strain and high vertical electric fields due to additive strain and
confined splitting, larger two-dimensional in-plane density of states,
and smaller conductivity mass.
2. Uniaxial stress-enhanced electron and hole mobilities mainly arise
from reduced conductivity effective mass vs. reduced scattering for
biaxial stress. Therefore, uniaxial stress provides larger drive current improvement for nanoscale short-channel devices with minimal increases in manufacturing complexity.
3. Uniaxial stress causes n-channel threshold voltage shifts that are
approximately five times smaller, and thus do not require adjustment in substrate doping.
4. Process-induced uniaxial stress increases with decreasing channel length.
5. A uniaxially strained device shows much better reliability.
6. Smaller leakages arise from reduced band gap narrowing, compared
with biaxial tensile stress, which causes much greater band-to-band
tunneling (BTBT) leakage.
7. Significantly less strain is required for hole mobility enhancement
when applying longitudinal uniaxial compression vs. in-plane biaxial tension using the conventional SiGe substrate approach. Therefore,
process-induced uniaxial stress is very promising for scaling down
CMOS technology per the goals of the proposed road map.
3.9 BEOL Stress: Through-Silicon Via
Stress has an impact on all of these reliability concerns. Back-end-of-the-line
(BEOL) stress is very important in terms of interconnect and dielectric reliability. Going toward the 32 nm node, a key challenge is BEOL integration.
In particular, dielectric reliability in the regime of low-k dielectrics is a major