70
Strain-Engineered MOSFETs
experiences an initial degradation at low Ge percentage, but then eventually
at Ge > 30%, it turns to mobility improvement. This hole mobility behaviour
is consistent with the classical piezoresistance theory. For mobility enhancement we consider two mechanisms: lowering of the in-plane effective mass
and reduced intervalley phonon scattering. Biaxial tensile strain (less than
< 1%) is not sufficient to reduce the in-plane hole effective mass. Moreover,
hole intervalley scattering is not significantly reduced either, since the band
splitting is less than the optical phonon energy. Thus, splitting greater than
60 meV and strain greater than 1% are necessary to suppress intervalley phonon scattering and to improve hole mobility. In order to achieve strain values
suitable for CMOS applications, it is necessary to use substrates with Ge content higher than 30%. However, high Ge concentration increases the defect
density in the Si layer and causes practical difficulties, such as controlling
threading dislocations in practical applications.
At present, mainly two approaches are being used in obtaining the desired
strain in CMOS technology. One is based on developing the strain at the substrate level before the transistor is built. This is known as the global approach,
for example, strained Si on relaxed SiGe virtual substrates. The approach
depends largely on materials engineering, rather than device design. Strained
Si, while promising, faces several key challenges. Minimising the number of
dislocations within the silicon will be important to keeping yield rates high.
Maintaining the level of strain during the manufacturing process is another
challenge. Also, a major drawback common to all global strain techniques for
CMOS technology is that they can provide only one type of strain.
Local strained Si technology is incorporated during the transistor fabrication process via tensile/compressive capping layers or recessed epitaxial film
deposition in the source/drain regions. These processes are not universal in
their implementation and can be modified to a particular transistor integration scheme. The straining technique based on process is known as processinduced strain, where stress is a specified zone or local in the transistor.
Process-induced uniaxial stress has advantages over biaxial stress, such as
larger mobility enhancements and a smaller shift in threshold voltage. The
local strain approach is found to be more promising in CMOS technology
and used for high-volume production. However, the drawback of processinduced strain techniques is their strong device geometry dependence, making the scaling behaviour less predictable. The following CMOS process steps
are mainly responsible for stress in the transistor channel: (1) shallow trench
isolation (STI), (2) silicidation at the source/drain region, and (3) nitride contact etch stop liners (CESLs). The local strain techniques have the following
advantages: (1) strain can be independently tailored to optimise performance
enhancement for both n- and p-MOSFETs, (2) the threshold voltage shift is
smaller in uniaxial stressed MOSFETs, (3) the stress memorisation, and (4)
cheaper and more compatible with standard CMOS technology.
Even though the predominant focus of the industry in the 1990s was on biaxial stressed devices, the current focus has shifted to uniaxial stress. Starting
Strain-Engineered MOSFETs
experiences an initial degradation at low Ge percentage, but then eventually
at Ge > 30%, it turns to mobility improvement. This hole mobility behaviour
is consistent with the classical piezoresistance theory. For mobility enhancement we consider two mechanisms: lowering of the in-plane effective mass
and reduced intervalley phonon scattering. Biaxial tensile strain (less than
< 1%) is not sufficient to reduce the in-plane hole effective mass. Moreover,
hole intervalley scattering is not significantly reduced either, since the band
splitting is less than the optical phonon energy. Thus, splitting greater than
60 meV and strain greater than 1% are necessary to suppress intervalley phonon scattering and to improve hole mobility. In order to achieve strain values
suitable for CMOS applications, it is necessary to use substrates with Ge content higher than 30%. However, high Ge concentration increases the defect
density in the Si layer and causes practical difficulties, such as controlling
threading dislocations in practical applications.
At present, mainly two approaches are being used in obtaining the desired
strain in CMOS technology. One is based on developing the strain at the substrate level before the transistor is built. This is known as the global approach,
for example, strained Si on relaxed SiGe virtual substrates. The approach
depends largely on materials engineering, rather than device design. Strained
Si, while promising, faces several key challenges. Minimising the number of
dislocations within the silicon will be important to keeping yield rates high.
Maintaining the level of strain during the manufacturing process is another
challenge. Also, a major drawback common to all global strain techniques for
CMOS technology is that they can provide only one type of strain.
Local strained Si technology is incorporated during the transistor fabrication process via tensile/compressive capping layers or recessed epitaxial film
deposition in the source/drain regions. These processes are not universal in
their implementation and can be modified to a particular transistor integration scheme. The straining technique based on process is known as processinduced strain, where stress is a specified zone or local in the transistor.
Process-induced uniaxial stress has advantages over biaxial stress, such as
larger mobility enhancements and a smaller shift in threshold voltage. The
local strain approach is found to be more promising in CMOS technology
and used for high-volume production. However, the drawback of processinduced strain techniques is their strong device geometry dependence, making the scaling behaviour less predictable. The following CMOS process steps
are mainly responsible for stress in the transistor channel: (1) shallow trench
isolation (STI), (2) silicidation at the source/drain region, and (3) nitride contact etch stop liners (CESLs). The local strain techniques have the following
advantages: (1) strain can be independently tailored to optimise performance
enhancement for both n- and p-MOSFETs, (2) the threshold voltage shift is
smaller in uniaxial stressed MOSFETs, (3) the stress memorisation, and (4)
cheaper and more compatible with standard CMOS technology.
Even though the predominant focus of the industry in the 1990s was on biaxial stressed devices, the current focus has shifted to uniaxial stress. Starting