68
Strain-Engineered MOSFETs
3.7 Stress Memorisation Technique (SMT)
Another way to obtain local strain is the stress memorisation technique (SMT).
The process consists of a few steps: poly-Si amorphisation, tensile CESL deposition, annealing, and liner removal. After recrystallisation, the poly-Si gate
preserves some of the stress condition, even when the tensile liner is removed
(Figure 3.12). This technique, although improving the performance of the
n-MOSFET devices, has a detrimental effect on the p-MOSFET devices. The
reason for this is not yet clearly understood.
Local strain can be applied to the channel through a stress memorisation
technique. In the conventional fabrication process, the S/D silicon area and
poly-gate are amorphised by S/D and extension implantation. In the SMT
process, a conventional dopant activation spike anneal is performed after the
deposition of a tensile capping layer, such as nitride. The stress effect is transferred from the nitride film to the channel during annealing and memorised
by the recrystallisation of the S/D and poly-gate amorphised layers. Since the
nitride film is disposable, a very thick capping layer can be used to increase
the stress level without any process limitation. The stress effect is transferred
from the nitride liner to the channel during annealing. After active area and
gate recrystallisation, the stress inside the channel is memorised, even when
the tensile liner is removed. The stress induced in the channel can be modulated by tuning many process parameters, such as amorphisation conditions,
nitride liner thickness and intrinsic stress, annealing conditions, etc. Up to
a 15% improvement in n-MOSFET drive current has been reported with the
0.2
–0.2
0
Silicon substrate
NiSi
NiSi
3.0E+09
StressXX
2.1E+09
1.1E+09
1.7E+08
–7.7E+08
–1.7E+09
X
0.2
Y
0
–0.2
FIGURE 3.11
Stress distributions after silicidation process. (After Maiti, T. K., Process-Induced Stress
Engineering in Silicon CMOS Technology, PhD thesis, Jadavpur University, 2009.)
Strain-Engineered MOSFETs
3.7 Stress Memorisation Technique (SMT)
Another way to obtain local strain is the stress memorisation technique (SMT).
The process consists of a few steps: poly-Si amorphisation, tensile CESL deposition, annealing, and liner removal. After recrystallisation, the poly-Si gate
preserves some of the stress condition, even when the tensile liner is removed
(Figure 3.12). This technique, although improving the performance of the
n-MOSFET devices, has a detrimental effect on the p-MOSFET devices. The
reason for this is not yet clearly understood.
Local strain can be applied to the channel through a stress memorisation
technique. In the conventional fabrication process, the S/D silicon area and
poly-gate are amorphised by S/D and extension implantation. In the SMT
process, a conventional dopant activation spike anneal is performed after the
deposition of a tensile capping layer, such as nitride. The stress effect is transferred from the nitride film to the channel during annealing and memorised
by the recrystallisation of the S/D and poly-gate amorphised layers. Since the
nitride film is disposable, a very thick capping layer can be used to increase
the stress level without any process limitation. The stress effect is transferred
from the nitride liner to the channel during annealing. After active area and
gate recrystallisation, the stress inside the channel is memorised, even when
the tensile liner is removed. The stress induced in the channel can be modulated by tuning many process parameters, such as amorphisation conditions,
nitride liner thickness and intrinsic stress, annealing conditions, etc. Up to
a 15% improvement in n-MOSFET drive current has been reported with the
0.2
–0.2
0
Silicon substrate
NiSi
NiSi
3.0E+09
StressXX
2.1E+09
1.1E+09
1.7E+08
–7.7E+08
–1.7E+09
X
0.2
Y
0
–0.2
FIGURE 3.11
Stress distributions after silicidation process. (After Maiti, T. K., Process-Induced Stress
Engineering in Silicon CMOS Technology, PhD thesis, Jadavpur University, 2009.)