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Process-Induced Stress Engineering in CMOS Technology
3.6 Silicidation
Another approach for introducing beneficial strain in p-MOSFET is by silicideinduced stress. Nickel-platinum silicide has been reported as an S/D material
for strain engineering in p-MOSFETs to improve drive current performance.
During the nickel-platinum silicidation process due to volume change and
reaction parameters, a compressive strain can be generated in the channel
region. The silicidation process incorporates a new element onto the growing
layer, and hence causes stress to build up when such layers are grown under
a lateral constraint. The silicide layers introduce a compressive strain on the
silicon channel [9]. Ti, Ni, and Co are some of the common metals used for
silicidation. Stress distribution after silicidation is shown in Figure 3.11.
Stress XX
–0.1
0.2
X (um)
0.1
0
Silicon substrate
Cap layer
–0.1
0
X (um)
0.1
2.6E+09
1.9E+09
1.2E+09
5.4E+08
–1.6E+08
–8.6E+08
FIGURE 3.10
Simulated XX component of stress tensor (σ xx ) of n-MOSFETs in channel with highly tensile cap
layer; distances are in micrometers. (After Maiti, T. K., Process-Induced Stress Engineering in
Silicon CMOS Technology, PhD thesis, Jadavpur University, 2009.)