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Strain-Engineered MOSFETs
Stressed liner technologies improve transistor mobility by depositing
a stressed nitride liner instead of a neutral liner on top of the gate and
spacers of a transistor. Depending on the technology, either a compressive
liner on top of p-MOSFET devices or a tensile liner on top of n-MOSFET
devices can be used, with the remaining device type having a neutral liner
on the top. The liner can be neutralised by doping. Dual-stress liner technology, on the other hand, uses both types of stressed liners and targets
to improve both n- and p-MOSFET mobilities at the same time. Looking
at the layout view, a p-MOSFET transistor is present on the left and an
n-MOSFET transistor is present on the right. In the side view, we can see
that p-MOSFET is covered with a compressive liner and n-MOSFET with
a tensile liner. The boundaries of these liners are defined by the dashed
lines in the layout view.
The next technique for creating uniaxial process-induced strain is the
use of a tensile or compressive stressed nitride capping layer. Nitride
films were among the first to be adapted for this application. By controlling the growth conditions, such as pressure, silicon nitride (SiN) layers
with more than 2GPa of tensile stress and more than 2.5GPa of compressive stress have recently been developed, simultaneously improving
n- and p-MOSFET performance with the so-called dual-stress liner (DSL)
technique. In this approach a Si 3 N 4 layer in a highly tensile stress state is
uniformly deposited over the entire wafer, followed by patterning and
etching the film off p-channel transistors. Thus, mechanical stress can be
transferred to the channel through the silicon active area and poly-gate if a
permanent stressed capping layer is deposited on a device. Since this layer
serves as a stopping layer for the contact etching between the first level
of metal and the transistor’s S/D and gate regions, it is also known as the
contact etch stop layer (CESL). CESL can contain up to 3 GPa of tensile or
compressive stress, depending on the deposition conditions, thus making
it an extremely effective and low-cost technique to introduce both longitudinal and out-of-plane channel stress. Similar to the e-SiGe technology,
which is used to generate a compressive channel stress in p-MOSFETs,
the CESL technology is a local stress technique. The stress in the MOSFET
channel due to CESL arises from two sources: thermal expansion coefficient mismatch between the silicon and nitride film and intrinsic film
stress caused by film shrinkage. A performance improvement of ~15% due
to tensile nitride films has been reported in the literature for n-MOSFETs.
The tensile stress distribution due to the nitride cap layer for n-MOSFET
is shown in Figure 3.10. If one single type of capping layer (tensile or compressive) is used, one drawback of this approach is that the device of the
opposite type will be degraded. To obtain better CMOS performance, two
types of stressed layers should be applied to p- and n-MOSFETs accordingly. A highly compressive and tensile nitride layer is used for p- and
n-MOSFETs, respectively.
Strain-Engineered MOSFETs
Stressed liner technologies improve transistor mobility by depositing
a stressed nitride liner instead of a neutral liner on top of the gate and
spacers of a transistor. Depending on the technology, either a compressive
liner on top of p-MOSFET devices or a tensile liner on top of n-MOSFET
devices can be used, with the remaining device type having a neutral liner
on the top. The liner can be neutralised by doping. Dual-stress liner technology, on the other hand, uses both types of stressed liners and targets
to improve both n- and p-MOSFET mobilities at the same time. Looking
at the layout view, a p-MOSFET transistor is present on the left and an
n-MOSFET transistor is present on the right. In the side view, we can see
that p-MOSFET is covered with a compressive liner and n-MOSFET with
a tensile liner. The boundaries of these liners are defined by the dashed
lines in the layout view.
The next technique for creating uniaxial process-induced strain is the
use of a tensile or compressive stressed nitride capping layer. Nitride
films were among the first to be adapted for this application. By controlling the growth conditions, such as pressure, silicon nitride (SiN) layers
with more than 2GPa of tensile stress and more than 2.5GPa of compressive stress have recently been developed, simultaneously improving
n- and p-MOSFET performance with the so-called dual-stress liner (DSL)
technique. In this approach a Si 3 N 4 layer in a highly tensile stress state is
uniformly deposited over the entire wafer, followed by patterning and
etching the film off p-channel transistors. Thus, mechanical stress can be
transferred to the channel through the silicon active area and poly-gate if a
permanent stressed capping layer is deposited on a device. Since this layer
serves as a stopping layer for the contact etching between the first level
of metal and the transistor’s S/D and gate regions, it is also known as the
contact etch stop layer (CESL). CESL can contain up to 3 GPa of tensile or
compressive stress, depending on the deposition conditions, thus making
it an extremely effective and low-cost technique to introduce both longitudinal and out-of-plane channel stress. Similar to the e-SiGe technology,
which is used to generate a compressive channel stress in p-MOSFETs,
the CESL technology is a local stress technique. The stress in the MOSFET
channel due to CESL arises from two sources: thermal expansion coefficient mismatch between the silicon and nitride film and intrinsic film
stress caused by film shrinkage. A performance improvement of ~15% due
to tensile nitride films has been reported in the literature for n-MOSFETs.
The tensile stress distribution due to the nitride cap layer for n-MOSFET
is shown in Figure 3.10. If one single type of capping layer (tensile or compressive) is used, one drawback of this approach is that the device of the
opposite type will be degraded. To obtain better CMOS performance, two
types of stressed layers should be applied to p- and n-MOSFETs accordingly. A highly compressive and tensile nitride layer is used for p- and
n-MOSFETs, respectively.