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Process-Induced Stress Engineering in CMOS Technology
been developed. A simplified representation of the main process flow steps for
dual-CESL deposition is shown in Figure 3.9. The main steps are
1. Depositing a tensile liner
2. Performing a lithography step to define the liner on the NMOS
3. Removing the etch liner from the PMOS
4. Post-etch strip
5. Depositing a compressive CESL liner
6. Performing a lithography step to define the compressive liner on
the PMOS
7. Removing the compressive liner from the NMOS
8. Post-etch strip
NMOS
Tensile liner deposition
Etch
Etch
Compressive liner deposition
PMOS
NMOS
P MOS
NMOS
P MOS
NMOS
P MOS
FIGURE 3.9
Simplified schematic diagrams of the main process flow steps for dual-CESL technology.
A tensile liner is deposited on top of the n-MOSFET and a compressive liner on top of the
p-MOSFET devices. (After Shickova, A., Bias Temperature Instability Effects in Devices
with Fully-Silicided Gate Stacks, Strained-Si, and Multiple-Gate Architectures, PhD thesis,
Katholieke Universiteit Leuven, 2008.)