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Process-Induced Stress Engineering in CMOS Technology
for drive current and enhanced electron mobility in n-MOSFETs. To give better device performance, SiGe or SiC, which is lattice mismatched to Si, can be
grown instead to induce strain in the channel for mobility improvement. In
addition, SiGe can also be exploited to lower the contact resistance due to the
smaller band gap of SiGe as Ge concentration increases.
3.4 Shallow Trench Isolation (STI)
Another technique, shallow trench isolation (STI), is normally used for lateral isolation between devices on the Si substrate. Shallow trench isolation is
an important and well-studied stress source that has not been fully exploited
until now for design quality improvement. STI usually exerts a compressive
stress along the channel (i.e., the current flow direction), which improves
p-MOSFET device mobility. The opposite type of stress, tensile stress,
degrades the p-MOSFET performance in this direction. The STI etch process
is used to create shallow trenches in the Si substrate, which are subsequently
filled with dielectric material to form isolation barriers between the STI edge
and the transistor region, creating a comprehensive channel between two
trench structures. Routine CMOS processing operations, such as isolation
formation, induce some strain in the silicon lattice. At STI, a large volume
of oxide is deposited in a trench to create isolation structures. The volume
contraction between the silicon and oxide results in stress from different
coefficients of thermal expansion. Residual stress can also arise if the wafer
is quenched (rapidly cooled), effectively locking a higher stress state oxide.
Further, densification of the oxide at high temperatures due to changes in
bonding can build up intrinsic residual stress in the STI oxides. This residual
stress is compressive for most commonly used oxide filling materials [9].
Since n-MOSFET performance improves in the presence of tensile strain,
recent efforts have focused on developing an STI process that results in
tensile strain in the channel. The strains created at the isolation edge
decay monotonically toward the middle of the channel, and the distance
between the gate edge and isolation edge determines the actual strain in
the channel. The larger the active area, the higher will be the impact of
the silicide stress, while the narrow-width devices show higher influence
of the STI stress. The magnitude of strain induced from the STI is typically lower than other forms of deliberate strain introduction. The popularly used BSIM SPICE model (revision 4.3 and higher) contains an explicit
STI model. However, only the impact of the distance from the transistor
channel to the STI boundary is modeled. Hence, the dependency on the
STI width is not present in the BSIM4 model. Our simulations, as well as
simulations and data in the literature [10], show that STIW impact cannot be neglected. Thus, as noted above, our present work not only models
Process-Induced Stress Engineering in CMOS Technology
for drive current and enhanced electron mobility in n-MOSFETs. To give better device performance, SiGe or SiC, which is lattice mismatched to Si, can be
grown instead to induce strain in the channel for mobility improvement. In
addition, SiGe can also be exploited to lower the contact resistance due to the
smaller band gap of SiGe as Ge concentration increases.
3.4 Shallow Trench Isolation (STI)
Another technique, shallow trench isolation (STI), is normally used for lateral isolation between devices on the Si substrate. Shallow trench isolation is
an important and well-studied stress source that has not been fully exploited
until now for design quality improvement. STI usually exerts a compressive
stress along the channel (i.e., the current flow direction), which improves
p-MOSFET device mobility. The opposite type of stress, tensile stress,
degrades the p-MOSFET performance in this direction. The STI etch process
is used to create shallow trenches in the Si substrate, which are subsequently
filled with dielectric material to form isolation barriers between the STI edge
and the transistor region, creating a comprehensive channel between two
trench structures. Routine CMOS processing operations, such as isolation
formation, induce some strain in the silicon lattice. At STI, a large volume
of oxide is deposited in a trench to create isolation structures. The volume
contraction between the silicon and oxide results in stress from different
coefficients of thermal expansion. Residual stress can also arise if the wafer
is quenched (rapidly cooled), effectively locking a higher stress state oxide.
Further, densification of the oxide at high temperatures due to changes in
bonding can build up intrinsic residual stress in the STI oxides. This residual
stress is compressive for most commonly used oxide filling materials [9].
Since n-MOSFET performance improves in the presence of tensile strain,
recent efforts have focused on developing an STI process that results in
tensile strain in the channel. The strains created at the isolation edge
decay monotonically toward the middle of the channel, and the distance
between the gate edge and isolation edge determines the actual strain in
the channel. The larger the active area, the higher will be the impact of
the silicide stress, while the narrow-width devices show higher influence
of the STI stress. The magnitude of strain induced from the STI is typically lower than other forms of deliberate strain introduction. The popularly used BSIM SPICE model (revision 4.3 and higher) contains an explicit
STI model. However, only the impact of the distance from the transistor
channel to the STI boundary is modeled. Hence, the dependency on the
STI width is not present in the BSIM4 model. Our simulations, as well as
simulations and data in the literature [10], show that STIW impact cannot be neglected. Thus, as noted above, our present work not only models