62
Strain-Engineered MOSFETs
3.3 Si 1–y C y in Source/Drain
SiC has been used in the source/drain regions to introduce stress locally for
device drive current enhancement. Figure 3.7 shows the transistor structure
with Si 1–y C y stressors in the source and drain regions. The SiC regions act as
stressors, giving rise to lateral tensile strain and vertical compressive strain
in the channel to enhance electron mobility. In addition, the SiC/strained Si
heterojunction at the source end of the transistor provides for enhanced electron injection velocity from the source. The theoretical limit of the channel
stress is determined by the maximum stress that can be generated at the Si/
SiC interface before dislocation is generated. The maximum stress depends
directly on the carbon mole fraction used. The partially relaxed SiC stressors
in the source and drain regions tensile strain the Si channel laterally, leading to a large tensile stress that extends throughout the channel region. It
has been observed that in the case of an anisotropic recess etch, for a given
carbon mole fraction the amount of stress in the channel is determined by
etch depth, which correlates to the SiC thickness, and the etch shape. The SiC
stressors affect two major strain components, the lateral stress and the vertical stress. The magnitude and distribution of stress components, the origin of
the stress field, and their relationship to electron mobility enhancement have
been discussed. It is shown that the strain effect due to the SiC S/D stressors as well as the increased electron injection velocity may play an important role at sub-100 nm gate lengths. Reducing the interstressor spacing and
increasing the C content and the recessed depth/raised height of the SiC
stressors are three ways to achieve high strain levels in the Si channel region
Si:C
Si:C
Drain
Source
Silicon
Gate
Vertical
Parallel
Perp.
FIGURE 3.7
Cross section of an n-MOSFET device with embedded SiC source/drain regions. The smaller
lattice of the SiC alloy results in tensile parallel stress in the channel of the device (After
Eneman, G., Design, Fabrication, and Characterization of Advanced Field Effect Transistors
with Strained Silicon Channels, PhD thesis, Katholieke Universiteit Leuven, 2006.)
Strain-Engineered MOSFETs
3.3 Si 1–y C y in Source/Drain
SiC has been used in the source/drain regions to introduce stress locally for
device drive current enhancement. Figure 3.7 shows the transistor structure
with Si 1–y C y stressors in the source and drain regions. The SiC regions act as
stressors, giving rise to lateral tensile strain and vertical compressive strain
in the channel to enhance electron mobility. In addition, the SiC/strained Si
heterojunction at the source end of the transistor provides for enhanced electron injection velocity from the source. The theoretical limit of the channel
stress is determined by the maximum stress that can be generated at the Si/
SiC interface before dislocation is generated. The maximum stress depends
directly on the carbon mole fraction used. The partially relaxed SiC stressors
in the source and drain regions tensile strain the Si channel laterally, leading to a large tensile stress that extends throughout the channel region. It
has been observed that in the case of an anisotropic recess etch, for a given
carbon mole fraction the amount of stress in the channel is determined by
etch depth, which correlates to the SiC thickness, and the etch shape. The SiC
stressors affect two major strain components, the lateral stress and the vertical stress. The magnitude and distribution of stress components, the origin of
the stress field, and their relationship to electron mobility enhancement have
been discussed. It is shown that the strain effect due to the SiC S/D stressors as well as the increased electron injection velocity may play an important role at sub-100 nm gate lengths. Reducing the interstressor spacing and
increasing the C content and the recessed depth/raised height of the SiC
stressors are three ways to achieve high strain levels in the Si channel region
Si:C
Si:C
Drain
Source
Silicon
Gate
Vertical
Parallel
Perp.
FIGURE 3.7
Cross section of an n-MOSFET device with embedded SiC source/drain regions. The smaller
lattice of the SiC alloy results in tensile parallel stress in the channel of the device (After
Eneman, G., Design, Fabrication, and Characterization of Advanced Field Effect Transistors
with Strained Silicon Channels, PhD thesis, Katholieke Universiteit Leuven, 2006.)