60
Strain-Engineered MOSFETs
FinFETs. Unlike the planar device, the major conducting surfaces of the
FinFET devices came from the sidewalls of the fin, having a surface orientation of (110). To exert a strain in the channel similar to that of the planar
2D devices, an embedded SiGe around the fin at the S/D regions is needed.
Local Ge condensation has been reported as an alternative technique for
the fabrication of embedded SiGe S/D stressors. It is reported that during the oxidation of the SiGe film, Ge is rejected from the oxide, and this
caused a pile-up of Ge at the interface between the top SiO 2 layer and SiGe.
Compressive stress is exerted on the channel from the SiGe S/D regions
on both the top and sidewalls. FinFETs with condensed SiGe S/D show a
higher drive current.
Two- and three-dimensional finite element (FE) methods are used to study
the stress and strain in the transistor structure. Lattice spacing of this Si 1–
x Ge x material is larger than silicon and results in uniaxial compressive strain
in the channel region, as shown in Figure 3.3. For p-MOSFET with Si 1–x Ge x
S/D, numerical simulation studies indicate that the magnitude of the lateral
compressive strain and the vertical tensile strain induced in the Si channel
can be increased by increasing the Ge mole fraction x in the Si 1–x Ge x S/D
region, by increasing the recess depth of the Si 1–x Ge x S/D, or by reducing
the separation between the Si 1–x Ge x S/D regions. The compressive stress is
mainly dependent on the e-SiGe thickness in the S/D, both below and above
(raised S/D) the Si surface, and Ge content in the SiGe. Too high a Ge content may cause defects and yield becomes an issue. Figure 3.5 shows the
simulated XX component of stress tensor (σ xx ) of p-MOSFETs in channel with
Si 0.83 Ge 0.17 pockets. For p-channel transistors, the SiGe source and drain (S/D)
stressor is commonly used to induce strain in the device channel. By making
use of the lattice mismatch between Si and SiGe, compressive strain can be
induced in the channel to enhance hole mobility. For enhanced strain effect,
a recess etch can be performed on the S/D region prior to the SiGe epitaxial
growth to realise embedded SiGe S/D stressors. Selective growth of SiC in
the source and drain has been used for n-MOSFET devices, and it is similar
to p-MOSFET with SiGe, but the recessed S/D is filled with SiC (inducing tensile strain). High C content and finding an optimised junction depth are two
important issues to obtain a maximum electron mobility enhancement. The
growth is somewhat more complicated due to low growth rates as a result
of chlorine-based chemistry to preserve the selectivity mode. The processinduced uniaxial compressive stress leads to drive current improvements of
up to 35% for PMOS transistors, which offers greater device performance.
Figure 3.6 shows a cross section of a transmission electron microscopy
(TEM) image of a PMOS test structure featuring an embedded SiGe source
and drain. For 20% Ge, compressive channel stresses on the order of ~1 GPa
are induced, depending on the proximity of the SiGe to the channel.
Strain-Engineered MOSFETs
FinFETs. Unlike the planar device, the major conducting surfaces of the
FinFET devices came from the sidewalls of the fin, having a surface orientation of (110). To exert a strain in the channel similar to that of the planar
2D devices, an embedded SiGe around the fin at the S/D regions is needed.
Local Ge condensation has been reported as an alternative technique for
the fabrication of embedded SiGe S/D stressors. It is reported that during the oxidation of the SiGe film, Ge is rejected from the oxide, and this
caused a pile-up of Ge at the interface between the top SiO 2 layer and SiGe.
Compressive stress is exerted on the channel from the SiGe S/D regions
on both the top and sidewalls. FinFETs with condensed SiGe S/D show a
higher drive current.
Two- and three-dimensional finite element (FE) methods are used to study
the stress and strain in the transistor structure. Lattice spacing of this Si 1–
x Ge x material is larger than silicon and results in uniaxial compressive strain
in the channel region, as shown in Figure 3.3. For p-MOSFET with Si 1–x Ge x
S/D, numerical simulation studies indicate that the magnitude of the lateral
compressive strain and the vertical tensile strain induced in the Si channel
can be increased by increasing the Ge mole fraction x in the Si 1–x Ge x S/D
region, by increasing the recess depth of the Si 1–x Ge x S/D, or by reducing
the separation between the Si 1–x Ge x S/D regions. The compressive stress is
mainly dependent on the e-SiGe thickness in the S/D, both below and above
(raised S/D) the Si surface, and Ge content in the SiGe. Too high a Ge content may cause defects and yield becomes an issue. Figure 3.5 shows the
simulated XX component of stress tensor (σ xx ) of p-MOSFETs in channel with
Si 0.83 Ge 0.17 pockets. For p-channel transistors, the SiGe source and drain (S/D)
stressor is commonly used to induce strain in the device channel. By making
use of the lattice mismatch between Si and SiGe, compressive strain can be
induced in the channel to enhance hole mobility. For enhanced strain effect,
a recess etch can be performed on the S/D region prior to the SiGe epitaxial
growth to realise embedded SiGe S/D stressors. Selective growth of SiC in
the source and drain has been used for n-MOSFET devices, and it is similar
to p-MOSFET with SiGe, but the recessed S/D is filled with SiC (inducing tensile strain). High C content and finding an optimised junction depth are two
important issues to obtain a maximum electron mobility enhancement. The
growth is somewhat more complicated due to low growth rates as a result
of chlorine-based chemistry to preserve the selectivity mode. The processinduced uniaxial compressive stress leads to drive current improvements of
up to 35% for PMOS transistors, which offers greater device performance.
Figure 3.6 shows a cross section of a transmission electron microscopy
(TEM) image of a PMOS test structure featuring an embedded SiGe source
and drain. For 20% Ge, compressive channel stresses on the order of ~1 GPa
are induced, depending on the proximity of the SiGe to the channel.