58
Strain-Engineered MOSFETs
Gate
Gate
SiGe
100 nm
Dislocation
Buffer
oxide NiSi x Ge 1–x
Void
Void
SWS
PMD 1
Si3N4
NiSi2
Si
Si recess etch
(a)
(b)
SiGe epitaxial growth
Tensile nitride
Compressive nitride
Gate
Gate
STI
NMOS
P MOS
STI
FIGURE 3.2
(a) Strained Si p-channel MOSFET process flow for the representative stacked gate transistor
and transmission electron microscopy cross-sectional view. (b) Dual-stress liner process architecture with tensile and compressive silicon nitride capping layers. (After Thompson, S. E., G.
Sun, Y. Choi, and T. Nishida, IEEE Trans. Electron Dev., 53, 1010–1020, 2006. With permission.)
Si 1–x Ge x
Si 1–x Ge x
Drain
Source
Silicon
Gate
Vertical
Parallel
Perp.
FIGURE 3.3
Cross section of a PMOS device with embedded Si 1–x Ge x source/drain regions. The bigger lattice of the Si 1–x Ge x alloy results in compressive parallel stress in the channel of the device. (After
Eneman, G., Design, Fabrication, and Characterization of Advanced Field Effect Transistors
with Strained Silicon Channels, PhD thesis, Katholieke Universiteit Leuven, 2006.)
Strain-Engineered MOSFETs
Gate
Gate
SiGe
100 nm
Dislocation
Buffer
oxide NiSi x Ge 1–x
Void
Void
SWS
PMD 1
Si3N4
NiSi2
Si
Si recess etch
(a)
(b)
SiGe epitaxial growth
Tensile nitride
Compressive nitride
Gate
Gate
STI
NMOS
P MOS
STI
FIGURE 3.2
(a) Strained Si p-channel MOSFET process flow for the representative stacked gate transistor
and transmission electron microscopy cross-sectional view. (b) Dual-stress liner process architecture with tensile and compressive silicon nitride capping layers. (After Thompson, S. E., G.
Sun, Y. Choi, and T. Nishida, IEEE Trans. Electron Dev., 53, 1010–1020, 2006. With permission.)
Si 1–x Ge x
Si 1–x Ge x
Drain
Source
Silicon
Gate
Vertical
Parallel
Perp.
FIGURE 3.3
Cross section of a PMOS device with embedded Si 1–x Ge x source/drain regions. The bigger lattice of the Si 1–x Ge x alloy results in compressive parallel stress in the channel of the device. (After
Eneman, G., Design, Fabrication, and Characterization of Advanced Field Effect Transistors
with Strained Silicon Channels, PhD thesis, Katholieke Universiteit Leuven, 2006.)