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Process-Induced Stress Engineering in CMOS Technology
low cost. In addition, typical process-induced strain technologies, such as
strained capping layer and embedded Si 1–x Ge x source/drain, are known to
generate uniaxial strain along the channel, which offers similar electron
mobility enhancement compared with biaxial strain, while the hole mobility
enhancement is retained at high E eff . The integration of SMT/DSL/e-SiGe has
been demonstrated in the literature for high-performance CMOS. Recently,
the stress proximity technique (SPT) for DSL has been successfully demonstrated by removing the spacer between the stressed liner and poly-gate to
maximise stress proximity. The integration of cost-effective techniques of
SMT/DSL/SPT has also been demonstrated. The various sources of processinduced stress are briefly described below.
3.2 Si 1–x Ge x in Source/Drain
Local strain in the device channel can be induced by substituting the Si in
the source/drain regions by a material with a different lattice constant. This
technique was first proposed by Intel as a strain technique for performance
enhancement. SiGe has been used in the past in the source and drain regions
for higher boron activation and reduced external resistance. Interestingly,
embedded SiGe at the source and drain has been recognised as one of the
options offering the best potential to enhance performance in sub-100 nm
technologies. This is based on a two-step process to form recessed junctions:
a dry or vapour etch of Si in S/D regions and a selective epitaxy growth of
B-doped SiGe layers (inducing compressive strain). The improvement of the
transistor performance is not only a mobility enhancement but also from
reduced S/D access resistance. Use of a lattice mismatched S/D stressor, such
as Si 1–x Ge x in the S/D region, is a very promising technique to introduce local
compressive strain in the channel region for p-MOSFET performance boost.
More than 50% enhancement in hole mobility over universal mobility can be
achieved with only a few key process steps added to the standard CMOS fabrication. In this case, strain is introduced from the stressor side using Si 1–x Ge x
in the source and drain region of the p-MOSFETs and Si 1–x C x for n-MOSFETs.
The Si 1–x Ge x in the source and drain process flow is simple, low in cost, and
solves the major issues associated with the biaxial strained silicon on the
relaxed Si 1–x Ge x buffer layer approach. Figure 3.2 shows the beneficial strain
components desired for improving hole mobility in a p-channel silicon transistor having a (001) channel surface and a source-to-drain direction oriented
along a [110] crystal direction.
Since in p-MOSFET devices, compressive parallel stress is beneficial
for hole mobility improvement, the Si in the S/D regions is substituted
by Si 1–x Ge x (see Figure 3.3). The larger lattice constant of Si 1–x Ge x creates a
compressive parallel stress inside the channel. The lattice constant of the
Process-Induced Stress Engineering in CMOS Technology
low cost. In addition, typical process-induced strain technologies, such as
strained capping layer and embedded Si 1–x Ge x source/drain, are known to
generate uniaxial strain along the channel, which offers similar electron
mobility enhancement compared with biaxial strain, while the hole mobility
enhancement is retained at high E eff . The integration of SMT/DSL/e-SiGe has
been demonstrated in the literature for high-performance CMOS. Recently,
the stress proximity technique (SPT) for DSL has been successfully demonstrated by removing the spacer between the stressed liner and poly-gate to
maximise stress proximity. The integration of cost-effective techniques of
SMT/DSL/SPT has also been demonstrated. The various sources of processinduced stress are briefly described below.
3.2 Si 1–x Ge x in Source/Drain
Local strain in the device channel can be induced by substituting the Si in
the source/drain regions by a material with a different lattice constant. This
technique was first proposed by Intel as a strain technique for performance
enhancement. SiGe has been used in the past in the source and drain regions
for higher boron activation and reduced external resistance. Interestingly,
embedded SiGe at the source and drain has been recognised as one of the
options offering the best potential to enhance performance in sub-100 nm
technologies. This is based on a two-step process to form recessed junctions:
a dry or vapour etch of Si in S/D regions and a selective epitaxy growth of
B-doped SiGe layers (inducing compressive strain). The improvement of the
transistor performance is not only a mobility enhancement but also from
reduced S/D access resistance. Use of a lattice mismatched S/D stressor, such
as Si 1–x Ge x in the S/D region, is a very promising technique to introduce local
compressive strain in the channel region for p-MOSFET performance boost.
More than 50% enhancement in hole mobility over universal mobility can be
achieved with only a few key process steps added to the standard CMOS fabrication. In this case, strain is introduced from the stressor side using Si 1–x Ge x
in the source and drain region of the p-MOSFETs and Si 1–x C x for n-MOSFETs.
The Si 1–x Ge x in the source and drain process flow is simple, low in cost, and
solves the major issues associated with the biaxial strained silicon on the
relaxed Si 1–x Ge x buffer layer approach. Figure 3.2 shows the beneficial strain
components desired for improving hole mobility in a p-channel silicon transistor having a (001) channel surface and a source-to-drain direction oriented
along a [110] crystal direction.
Since in p-MOSFET devices, compressive parallel stress is beneficial
for hole mobility improvement, the Si in the S/D regions is substituted
by Si 1–x Ge x (see Figure 3.3). The larger lattice constant of Si 1–x Ge x creates a
compressive parallel stress inside the channel. The lattice constant of the