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Process-Induced Stress Engineering in CMOS Technology
The technique for local strain introduction for both n- and p-MOSFET devices
is the contact etch stop layer (CESL). It consists of a nitride liner, deposited over
the devices. By tuning the process parameters, the type and level of the intrinsic stress of the liner can be determined. The so-called dual-CESL approach
consists of depositing a CESL liner with tensile stress over the n-MOSFET
devices and a liner with compressive stress over the p-MOSFET devices, thus
improving both electron and hole mobility at the same time. This makes the
dual-CESL approach one of the leading candidates for the CMOS industry.
Major techniques to introduce uniaxial stress include embedded SiGe
(e-SiGe) technology, dual-stress liner (DSL), stress memorisation technique
(SMT), and the parasitic stress from shallow trench isolation (STI). Embedded
SiGe in the source and drain area is used to introduce compressive stress for
p-MOSFET. DSL introduces the stress by depositing a highly stressed silicon
nitride layer, tensile stress for the n-MOSFET region, and compressive stress
for the p-MOSFET region, over the entire wafer to elevate carrier mobility.
In SMT, the stress in the channel is transferred from the stressed deposited
dielectric and is memorised during the recrystallisation of the active area
and poly-gate when thermal annealing is activated. STI stress results from
the difference in thermal expansion coefficients between SiO 2 and Si. It is an
intrinsic stress source and not intentionally built up for enhancing device
performance enhancement. The purpose of this chapter is to briefly review
the currently used promising strain techniques to fabricate strained silicon
transistors, and to assess their opportunities, as well as their technological
limitations. Strain induced by epitaxial Si 1–x Ge x in the source/drain regions
and strained contact etch stop layers (CESLs) are covered. Layout dependence of the Si 1–x Ge x S/D and strained CESL technologies are discussed.
3.1 Stress Engineering
An engineered substrate is a semiconductor material that can be fabricated
and introduced in the conventional silicon manufacturing, resulting in products that are unique and could not have been fabricated using only silicon
substrate. The introduction of strain changes the mechanical, electrical (band
structure and mobility), and chemical (diffusion and activation) properties
of a semiconductor. The various effects of stress and strain on silicon and
also silicon technology have been studied since 1950s [4, 5]. Most significant
to silicon technology are the changes in band gap, effective mass, mobility,
diffusivity of dopants, and oxidation rates. The effects of strain on mobility
were found to be anisotropic, and carrier effects were found to be different
for bulk silicon and inversion layers [6, 7].
Classification of strain techniques currently in use can be made in two
main categories. Strain is introduced across the entire substrate in global
Process-Induced Stress Engineering in CMOS Technology
The technique for local strain introduction for both n- and p-MOSFET devices
is the contact etch stop layer (CESL). It consists of a nitride liner, deposited over
the devices. By tuning the process parameters, the type and level of the intrinsic stress of the liner can be determined. The so-called dual-CESL approach
consists of depositing a CESL liner with tensile stress over the n-MOSFET
devices and a liner with compressive stress over the p-MOSFET devices, thus
improving both electron and hole mobility at the same time. This makes the
dual-CESL approach one of the leading candidates for the CMOS industry.
Major techniques to introduce uniaxial stress include embedded SiGe
(e-SiGe) technology, dual-stress liner (DSL), stress memorisation technique
(SMT), and the parasitic stress from shallow trench isolation (STI). Embedded
SiGe in the source and drain area is used to introduce compressive stress for
p-MOSFET. DSL introduces the stress by depositing a highly stressed silicon
nitride layer, tensile stress for the n-MOSFET region, and compressive stress
for the p-MOSFET region, over the entire wafer to elevate carrier mobility.
In SMT, the stress in the channel is transferred from the stressed deposited
dielectric and is memorised during the recrystallisation of the active area
and poly-gate when thermal annealing is activated. STI stress results from
the difference in thermal expansion coefficients between SiO 2 and Si. It is an
intrinsic stress source and not intentionally built up for enhancing device
performance enhancement. The purpose of this chapter is to briefly review
the currently used promising strain techniques to fabricate strained silicon
transistors, and to assess their opportunities, as well as their technological
limitations. Strain induced by epitaxial Si 1–x Ge x in the source/drain regions
and strained contact etch stop layers (CESLs) are covered. Layout dependence of the Si 1–x Ge x S/D and strained CESL technologies are discussed.
3.1 Stress Engineering
An engineered substrate is a semiconductor material that can be fabricated
and introduced in the conventional silicon manufacturing, resulting in products that are unique and could not have been fabricated using only silicon
substrate. The introduction of strain changes the mechanical, electrical (band
structure and mobility), and chemical (diffusion and activation) properties
of a semiconductor. The various effects of stress and strain on silicon and
also silicon technology have been studied since 1950s [4, 5]. Most significant
to silicon technology are the changes in band gap, effective mass, mobility,
diffusivity of dopants, and oxidation rates. The effects of strain on mobility
were found to be anisotropic, and carrier effects were found to be different
for bulk silicon and inversion layers [6, 7].
Classification of strain techniques currently in use can be made in two
main categories. Strain is introduced across the entire substrate in global