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Strain-Engineered MOSFETs
in CMOS technology [1]. It improves the electron mobility, but degrades the
hole mobility at low-stress range (<500 MPa). Since 2003, uniaxial stress has
been applied to Intel’s 90, 65, 45, and 22 nm technologies to improve the drive
current without significantly increased manufacturing complexity [2, 3].
Advanced CMOS technologies feature multiple process-induced stressors
such as compressive and tensile overlayers, embedded SiGe (e-SiGe), and
multiple stress memorisation techniques. Large magnitudes of uniaxial
channel stress (~1 GPa) are being incorporated in p-channel devices of the
65 nm technology node, and an even higher stress level is necessary in the
32 nm technology node. Local strain approaches are based on dedicated processing steps or process modules such as shallow trench isolation, silicidation or metal gate electrodes, the use of liners and capping layers, dry etch
processes, contact etch stop layers, and source/drain (S/D) engineering.
Extension of CMOS beyond 22 nm technology nodes will require new nonclassical MOSFET structures coupled with advanced materials and processes.
Classes of new materials include high-k gate dielectrics, metal and mid-gap
gate metal electrodes, strained Si, and silicon-germanium alloys. These new
materials will lower the gate leakage current and gate resistance, reduce the
poly-gate electrode depletion capacitance, and increase the device speed.
Nonclassical CMOS structures offer better control of short-channel effects,
improved ON current via higher channel mobility, lower load capacitance,
and lower propagation delay time. Besides scaling, several innovative mobility enhancement techniques are being attempted to maintain the CMOS
performance improvement. Mobility enhancement is attractive because it
improves device performance without device scaling. However, continued
miniaturisation increases device complexity and internal mechanical stress.
Changes in electron and hole mobility due to stress from local oxidation
of silicon (LOCOS) and shallow trench isolation have been known for a long
time. But because the strain from a localised source decays rapidly away
from the stressor, it could not be used as a strain technique until deep submicrometer technologies were developed. Stress or strain changes the band
structure of a semiconductor, which in turn changes other material properties, such as band gap, effective mass, carrier mobility, diffusivity of dopants,
and oxidation rates. When applied in the direction of the channel (for standard wafer orientation), tensile strain is used to improve the electron mobility in n-MOSFETs, while compressive strain is beneficial for hole mobility
improvement in p-MOSFETs.
One example of the local strain approach is to integrate epitaxially grown
SiGe into the source and drain regions. A compressive stress in the direction of the device channel can be generated, if SiGe with its larger lattice
constant is grown epitaxially on silicon. However, this approach can only
be used for enhancement of p-MOSFET devices. For n-MOSFET devices,
a similar effect can be achieved by epitaxially growing a material with a
smaller crystal lattice, such as carbon-doped silicon (SiC), into the source
and drain regions.
Strain-Engineered MOSFETs
in CMOS technology [1]. It improves the electron mobility, but degrades the
hole mobility at low-stress range (<500 MPa). Since 2003, uniaxial stress has
been applied to Intel’s 90, 65, 45, and 22 nm technologies to improve the drive
current without significantly increased manufacturing complexity [2, 3].
Advanced CMOS technologies feature multiple process-induced stressors
such as compressive and tensile overlayers, embedded SiGe (e-SiGe), and
multiple stress memorisation techniques. Large magnitudes of uniaxial
channel stress (~1 GPa) are being incorporated in p-channel devices of the
65 nm technology node, and an even higher stress level is necessary in the
32 nm technology node. Local strain approaches are based on dedicated processing steps or process modules such as shallow trench isolation, silicidation or metal gate electrodes, the use of liners and capping layers, dry etch
processes, contact etch stop layers, and source/drain (S/D) engineering.
Extension of CMOS beyond 22 nm technology nodes will require new nonclassical MOSFET structures coupled with advanced materials and processes.
Classes of new materials include high-k gate dielectrics, metal and mid-gap
gate metal electrodes, strained Si, and silicon-germanium alloys. These new
materials will lower the gate leakage current and gate resistance, reduce the
poly-gate electrode depletion capacitance, and increase the device speed.
Nonclassical CMOS structures offer better control of short-channel effects,
improved ON current via higher channel mobility, lower load capacitance,
and lower propagation delay time. Besides scaling, several innovative mobility enhancement techniques are being attempted to maintain the CMOS
performance improvement. Mobility enhancement is attractive because it
improves device performance without device scaling. However, continued
miniaturisation increases device complexity and internal mechanical stress.
Changes in electron and hole mobility due to stress from local oxidation
of silicon (LOCOS) and shallow trench isolation have been known for a long
time. But because the strain from a localised source decays rapidly away
from the stressor, it could not be used as a strain technique until deep submicrometer technologies were developed. Stress or strain changes the band
structure of a semiconductor, which in turn changes other material properties, such as band gap, effective mass, carrier mobility, diffusivity of dopants,
and oxidation rates. When applied in the direction of the channel (for standard wafer orientation), tensile strain is used to improve the electron mobility in n-MOSFETs, while compressive strain is beneficial for hole mobility
improvement in p-MOSFETs.
One example of the local strain approach is to integrate epitaxially grown
SiGe into the source and drain regions. A compressive stress in the direction of the device channel can be generated, if SiGe with its larger lattice
constant is grown epitaxially on silicon. However, this approach can only
be used for enhancement of p-MOSFET devices. For n-MOSFET devices,
a similar effect can be achieved by epitaxially growing a material with a
smaller crystal lattice, such as carbon-doped silicon (SiC), into the source
and drain regions.