53
3
Process-Induced Stress Engineering
in CMOS Technology
For more than four decades the rapid progress in complementary metaloxide-semiconductor (CMOS) technology has taken place through the tremendous pace of scaling, leading to an enormous increase in speed and
functionality of electronic devices. However, it is getting extremely difficult
to meet metal-oxide-semiconductor field-effect transistor (MOSFET) performance gains with acceptable device leakage. Now the gate leakage current
constitutes a major part of the power budget of microprocessors. Another
critical scaling issue involved is the increase of the source/drain series resistance resulting from the ultra-shallow p-n junctions in the source/drain
regions. To keep the source/drain series resistance at a reasonable fraction
of the total channel resistance (~10%), several alternative MOSFET structures
have been proposed, such as nonoverlapped gate structures, which do not
require ultra-shallow source/drain junctions or structures with metallic
source and drain electrodes to minimise the series resistance. Advanced
multigate structures, such as FinFETs and ultra-thin-body (UTB) MOSFETs,
may provide a path toward scaling CMOS to the end of the ITRS road map.
Stress and strain engineering are the key elements in current CMOS technologies and can accommodate nonclassical CMOS structures.
Starting at the 65 nm node, stress engineering to improve performance
of transistors has been a major industry focus. In order to induce appropriate strain in the channel region of MOSFETs, various techniques have been
introduced, such as substrate-induced strain, process-induced strain, and
bending-induced strain. The epitaxially grown Si on a relaxed Si 1–x Ge x layer
is a typical example of substrate-induced strain. The lattice of the Si layer is
stretched (biaxial tensile strain) in the plane of the interface due to the lattice mismatch between Si and Si 1–x Ge x . By increasing Ge mole fraction (x),
more biaxial tensile strain in the Si layer is induced as long as its thickness is
under critical thickness. However, strain relaxation during high-temperature
processes and high defect density (e.g., misfit and threading dislocations)
remain issues for production. In addition, the hole mobility enhancement is
reduced at high electric field for biaxial tensile strain. Recent attention has
shifted to process-induced uniaxial strain as uniaxial compressive strain
along a <110> channel enhances hole mobility even at high vertical fields.
Strain is one key feature to enhance the performance of Si MOSFETs. Biaxial
tensile strain has been investigated both experimentally and theoretically
3
Process-Induced Stress Engineering
in CMOS Technology
For more than four decades the rapid progress in complementary metaloxide-semiconductor (CMOS) technology has taken place through the tremendous pace of scaling, leading to an enormous increase in speed and
functionality of electronic devices. However, it is getting extremely difficult
to meet metal-oxide-semiconductor field-effect transistor (MOSFET) performance gains with acceptable device leakage. Now the gate leakage current
constitutes a major part of the power budget of microprocessors. Another
critical scaling issue involved is the increase of the source/drain series resistance resulting from the ultra-shallow p-n junctions in the source/drain
regions. To keep the source/drain series resistance at a reasonable fraction
of the total channel resistance (~10%), several alternative MOSFET structures
have been proposed, such as nonoverlapped gate structures, which do not
require ultra-shallow source/drain junctions or structures with metallic
source and drain electrodes to minimise the series resistance. Advanced
multigate structures, such as FinFETs and ultra-thin-body (UTB) MOSFETs,
may provide a path toward scaling CMOS to the end of the ITRS road map.
Stress and strain engineering are the key elements in current CMOS technologies and can accommodate nonclassical CMOS structures.
Starting at the 65 nm node, stress engineering to improve performance
of transistors has been a major industry focus. In order to induce appropriate strain in the channel region of MOSFETs, various techniques have been
introduced, such as substrate-induced strain, process-induced strain, and
bending-induced strain. The epitaxially grown Si on a relaxed Si 1–x Ge x layer
is a typical example of substrate-induced strain. The lattice of the Si layer is
stretched (biaxial tensile strain) in the plane of the interface due to the lattice mismatch between Si and Si 1–x Ge x . By increasing Ge mole fraction (x),
more biaxial tensile strain in the Si layer is induced as long as its thickness is
under critical thickness. However, strain relaxation during high-temperature
processes and high defect density (e.g., misfit and threading dislocations)
remain issues for production. In addition, the hole mobility enhancement is
reduced at high electric field for biaxial tensile strain. Recent attention has
shifted to process-induced uniaxial strain as uniaxial compressive strain
along a <110> channel enhances hole mobility even at high vertical fields.
Strain is one key feature to enhance the performance of Si MOSFETs. Biaxial
tensile strain has been investigated both experimentally and theoretically