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Substrate-Induced Strain Engineering in CMOS Technology
in the strained Si as well as band offsets between the relaxed Si l–x Ge x and
the strained Si, which can be used for carrier confinement in advanced
device structures. Surface channel strained Si p- and n-MOSFETs with varying strain in the Si layer were discussed.
A variety of strained Si on relaxed Si l–x Ge x heterostructure architectures
for p- and n-MOSFETs have been considered in order to study the carrier
transport. The nature of the carrier mobility enhancement in the strained
Si n- and p-MOSFETs has been discussed. A broad range of experimental
techniques used for the growth of the films, the effect of various fabrication
processes, and the electronic properties of the resulting structures have been
covered. In addition to clearly demonstrating enhanced device performance
in long-channel MOSFETs, several important physical characteristics of the
strained Si material itself were also discussed.
Review Questions
1. What is substrate-induced strain?
2. What are the effects of strain on mobility?
3. Electron mobility is increased by the degeneracy splitting of the conduction band minimum. (True/False)
4. MOSFET performance is degraded at high vertical electric fields.
(True/False)
5. What is biaxial strain?
6. What is uniaxial strain?
7. What are the differences between biaxial and uniaxial strain?
8. How can strain be introduced in a semiconductor?
9. What are the two main strain technologies being used in CMOS
fabrication?
10. What is hybrid orientation technology?
11. What is process-induced strain?
12. What is critical layer thickness?
13. What is band gap engineering?
14. What is Vegard’s rule?
15. What happens when one deposits film beyond a critical layer thickness?
16. What is SSOI?
17. What is the use of the relaxed SiGe buffer layer?
Substrate-Induced Strain Engineering in CMOS Technology
in the strained Si as well as band offsets between the relaxed Si l–x Ge x and
the strained Si, which can be used for carrier confinement in advanced
device structures. Surface channel strained Si p- and n-MOSFETs with varying strain in the Si layer were discussed.
A variety of strained Si on relaxed Si l–x Ge x heterostructure architectures
for p- and n-MOSFETs have been considered in order to study the carrier
transport. The nature of the carrier mobility enhancement in the strained
Si n- and p-MOSFETs has been discussed. A broad range of experimental
techniques used for the growth of the films, the effect of various fabrication
processes, and the electronic properties of the resulting structures have been
covered. In addition to clearly demonstrating enhanced device performance
in long-channel MOSFETs, several important physical characteristics of the
strained Si material itself were also discussed.
Review Questions
1. What is substrate-induced strain?
2. What are the effects of strain on mobility?
3. Electron mobility is increased by the degeneracy splitting of the conduction band minimum. (True/False)
4. MOSFET performance is degraded at high vertical electric fields.
(True/False)
5. What is biaxial strain?
6. What is uniaxial strain?
7. What are the differences between biaxial and uniaxial strain?
8. How can strain be introduced in a semiconductor?
9. What are the two main strain technologies being used in CMOS
fabrication?
10. What is hybrid orientation technology?
11. What is process-induced strain?
12. What is critical layer thickness?
13. What is band gap engineering?
14. What is Vegard’s rule?
15. What happens when one deposits film beyond a critical layer thickness?
16. What is SSOI?
17. What is the use of the relaxed SiGe buffer layer?