46
Strain-Engineered MOSFETs
0.0
200
250
300
Electron Mobility (cm –2
V –1
S –1
)
350
400
3.0×10 12
HOT nFET on (100) epi-Si
Control nFET on (100) SOI
6.0×10 12
N inv (cm –2 )
9.0×10 12
0.0
0
50
100
Hole Mobility (cm 2
V –1
S –1
)
200
150
250
5.0×10 12
HOT pFET on (110) epi-Si
Control pFET on (100) bulk substrate
1.0×10 13
N inv (cm –2 )
FIGURE 2.22
Electron (left) and hole (right) mobility measured on MOSFETs fabricated on (100) epi-Si on a
HOT-A substrate and (110) epi-Si on a HOT-B substrate, respectively. (After Yang, M., V. W. C.
Chan, K. K. Chan, L. Shi, D. M. Fried, J. H. Stahis, A. I. Chou, E. Gusev, J. A. Ott, L. E. Burns, and
M. V. Fischetti, IEEE Trans. Electron Dev., 53, 965–978, 2006. With permission.)
FIGURE 2.21
Integrated process flow for the HOT CMOS fabrication on a hybrid orientation substrate,
where n-MOSFET is on the (100) surface and p-MOSFET is on the (110) surface. (After Yang, M.,
V. W. C. Chan, K. K. Chan, L. Shi, D. M. Fried, J. H. Stahis, A. I. Chou, E. Gusev, J. A. Ott, L. E.
Burns, and M. V. Fischetti, IEEE Trans. Electron Dev., 53, 965–978, 2006. With permission.)