44
Strain-Engineered MOSFETs
2.10 Hybrid Orientation Technology
The electrical properties of Si are highly dependent on the crystal orientation
and the direction of the carrier transport. Furthermore, hole and electron
mobility are not maximised in the same direction and orientation. Besides
substrate-induced and process-induced stress engineering, wafer substrate
orientation and channel orientation can improve mobility. Different surface
orientations and directions of applied field for different in-plane stresses
provide different interactions with carrier transport. The strained Si technologies discussed so far assumed the standard (100) Si substrate for improving the carrier mobilities. Since the carrier mobilities are dependent on the
crystal orientation of the substrate as well as the direction of the channel [13],
the mobilities can be further enhanced by adopting different substrate orientations and channel directions. Maximum benefit in CMOS performance
can be drawn when the n- and p-MOSFET transistors are grown on (100) and
(110) substrate orientations, respectively, with [110] as the channel direction.
Combining the benefits of this hybrid orientation technology (HOT) on SOI
with the stress induced from processing steps, significant improvements in
p-MOSFET mobility have been reported [14].
An alternative approach yielding mobility improvement in Si exploits the
dependence of the carrier mobility in Si inversion layers on the crystal orientation and on the current flow direction. For example, for holes the mobility
is 2.5 times higher for (110) surface orientation than for standard (001) orientation, depending on the applied effective vertical field. In HOT, which is based
on wafer bonding techniques and selective epitaxy, the larger carrier mobility of holes for (110)-oriented substrate is exploited to enhance the performance of p-channel MOSFETs. HOT seems promising because processes are
directly compatible with existing CMOS technology and strain engineering.
Yang et al. [14] have developed a novel planar silicon CMOS structure: HOT
comprised of n-MOSFETs on silicon of (100) surface orientation and p-MOSFETs on (110) surface orientation (see Figure 2.19). A schematic cross section
of CMOS on the hybrid orientation substrate is shown in Figure 2.20. HOT
includes two types: type A with p-MOSFET on the (110) SOI and n-MOSFET
on the (100) silicon epitaxial layer, and type B with n-MOSFET on the (100)
SOI and p-MOSFET on the (110) silicon epitaxial layer.
The integrated process flow for the HOT CMOS fabrication is shown in
Figure 2.21. It is found that electron mobility on the (100) epi-Si can be even
slightly better than that on the (100) control substrate, and hole mobility on
(110) epi-Si is 2.5 times that on the (100) control (Figure 2.22), similar to that
observed on the (110) bulk substrate.
Figure 2.23 shows the drive current of large-width p-MOSFETs on (110) epitaxial silicon at –1.0 V supply voltage. p-MOSFET drive current is improved
by 29% in the <110> direction from the compressive stress at I off = 100 nA/μm,
and little effect is observed when the current flow direction changes to <100>.
Strain-Engineered MOSFETs
2.10 Hybrid Orientation Technology
The electrical properties of Si are highly dependent on the crystal orientation
and the direction of the carrier transport. Furthermore, hole and electron
mobility are not maximised in the same direction and orientation. Besides
substrate-induced and process-induced stress engineering, wafer substrate
orientation and channel orientation can improve mobility. Different surface
orientations and directions of applied field for different in-plane stresses
provide different interactions with carrier transport. The strained Si technologies discussed so far assumed the standard (100) Si substrate for improving the carrier mobilities. Since the carrier mobilities are dependent on the
crystal orientation of the substrate as well as the direction of the channel [13],
the mobilities can be further enhanced by adopting different substrate orientations and channel directions. Maximum benefit in CMOS performance
can be drawn when the n- and p-MOSFET transistors are grown on (100) and
(110) substrate orientations, respectively, with [110] as the channel direction.
Combining the benefits of this hybrid orientation technology (HOT) on SOI
with the stress induced from processing steps, significant improvements in
p-MOSFET mobility have been reported [14].
An alternative approach yielding mobility improvement in Si exploits the
dependence of the carrier mobility in Si inversion layers on the crystal orientation and on the current flow direction. For example, for holes the mobility
is 2.5 times higher for (110) surface orientation than for standard (001) orientation, depending on the applied effective vertical field. In HOT, which is based
on wafer bonding techniques and selective epitaxy, the larger carrier mobility of holes for (110)-oriented substrate is exploited to enhance the performance of p-channel MOSFETs. HOT seems promising because processes are
directly compatible with existing CMOS technology and strain engineering.
Yang et al. [14] have developed a novel planar silicon CMOS structure: HOT
comprised of n-MOSFETs on silicon of (100) surface orientation and p-MOSFETs on (110) surface orientation (see Figure 2.19). A schematic cross section
of CMOS on the hybrid orientation substrate is shown in Figure 2.20. HOT
includes two types: type A with p-MOSFET on the (110) SOI and n-MOSFET
on the (100) silicon epitaxial layer, and type B with n-MOSFET on the (100)
SOI and p-MOSFET on the (110) silicon epitaxial layer.
The integrated process flow for the HOT CMOS fabrication is shown in
Figure 2.21. It is found that electron mobility on the (100) epi-Si can be even
slightly better than that on the (100) control substrate, and hole mobility on
(110) epi-Si is 2.5 times that on the (100) control (Figure 2.22), similar to that
observed on the (110) bulk substrate.
Figure 2.23 shows the drive current of large-width p-MOSFETs on (110) epitaxial silicon at –1.0 V supply voltage. p-MOSFET drive current is improved
by 29% in the <110> direction from the compressive stress at I off = 100 nA/μm,
and little effect is observed when the current flow direction changes to <100>.