43
Substrate-Induced Strain Engineering in CMOS Technology
leakage, and (3) recombination of free carriers by trap states created from
the dislocations, resulting in a lower current density of devices. However, it
has been demonstrated experimentally that the hole mobility is improved
in strained Si. The enhancement in the hole mobility was found to be 40% at
room temperature and 200% at 77 K [12]. However, the ability to achieve both
n- and p-MOSFET devices using strained Si provides a promising alternative
for next generation high-performance SiGe CMOS technology.
The thermal conductivity of the underlying SiGe is at least 15 times lower
than that of the bulk Si. Thus, in the case of a strained Si MOSFET, the SiGe
layer basically confines the generated heat to the top layer of Si. This is analogous to the self-heating effect in silicon-on-insulator, and it will degrade the
drive current. Due to self-heating, strain relaxation could also result, which
may affect the drain current enhancement. From a reliability perspective,
the degradation mechanism could be very sensitive to the transistor temperature. At high drain voltage, the heat is readily dissipated in the case
of a bulk Si transistor, and hence there is a negligible difference between
the drain current measured by the DC technique and that by the AC technique. In contrast, the drain current of the strained Si transistor measured
by the DC technique is degraded under high drain voltage bias due to the
low heat dissipation efficiency. As the AC measurement setup could relieve
part of the heating process, some drain current enhancement would then
be observed. The presence of self-heating effect is also confirmed by other
measurement techniques. From the hot-carrier reliability perspective, the
degradation mechanism could be very sensitive to the transistor temperature in the strained Si.
Strained Si quantum wells (QWs) on relaxed SiGe layers, generally known
as relaxed buffer layers (also called virtual substrates), can be used for both
n- and p-MOSFETs. Moreover, these virtual substrates are of great interest for
integrating Si-based devices with III-V semiconductor devices to utilise their
optical properties [1]. Very high electron mobilities demonstrated in strained
Si layers suggest a great potential for this material in high-transconductance
n-MOSFETs. To date, in-plane electron mobilities approaching 3,000 cm 2 /Vs
have been reported in long-channel MOSFETs with both surface and buried
channels.
Due to its enhanced current drive and high-frequency performance,
strained Si technology is undoubtedly one of the enabling technologies
for RF circuit applications. Although the enhanced cutoff frequency of the
strained Si MOSFET can facilitate the RF CMOS circuit design, the unintentionally induced threading dislocations in the strained Si channel can potentially degrade some RF circuits. Enhanced drive currents of 15 to 25% have
been demonstrated on sub-100 nm bulk strained silicon MOSFETs. However,
it has been difficult to implement because of misfit and threading dislocations, Ge outdiffusion, silicide formation difficulty, self-heating effect, higher
arsenic diffusion in the S/D extension region, and cost.
Substrate-Induced Strain Engineering in CMOS Technology
leakage, and (3) recombination of free carriers by trap states created from
the dislocations, resulting in a lower current density of devices. However, it
has been demonstrated experimentally that the hole mobility is improved
in strained Si. The enhancement in the hole mobility was found to be 40% at
room temperature and 200% at 77 K [12]. However, the ability to achieve both
n- and p-MOSFET devices using strained Si provides a promising alternative
for next generation high-performance SiGe CMOS technology.
The thermal conductivity of the underlying SiGe is at least 15 times lower
than that of the bulk Si. Thus, in the case of a strained Si MOSFET, the SiGe
layer basically confines the generated heat to the top layer of Si. This is analogous to the self-heating effect in silicon-on-insulator, and it will degrade the
drive current. Due to self-heating, strain relaxation could also result, which
may affect the drain current enhancement. From a reliability perspective,
the degradation mechanism could be very sensitive to the transistor temperature. At high drain voltage, the heat is readily dissipated in the case
of a bulk Si transistor, and hence there is a negligible difference between
the drain current measured by the DC technique and that by the AC technique. In contrast, the drain current of the strained Si transistor measured
by the DC technique is degraded under high drain voltage bias due to the
low heat dissipation efficiency. As the AC measurement setup could relieve
part of the heating process, some drain current enhancement would then
be observed. The presence of self-heating effect is also confirmed by other
measurement techniques. From the hot-carrier reliability perspective, the
degradation mechanism could be very sensitive to the transistor temperature in the strained Si.
Strained Si quantum wells (QWs) on relaxed SiGe layers, generally known
as relaxed buffer layers (also called virtual substrates), can be used for both
n- and p-MOSFETs. Moreover, these virtual substrates are of great interest for
integrating Si-based devices with III-V semiconductor devices to utilise their
optical properties [1]. Very high electron mobilities demonstrated in strained
Si layers suggest a great potential for this material in high-transconductance
n-MOSFETs. To date, in-plane electron mobilities approaching 3,000 cm 2 /Vs
have been reported in long-channel MOSFETs with both surface and buried
channels.
Due to its enhanced current drive and high-frequency performance,
strained Si technology is undoubtedly one of the enabling technologies
for RF circuit applications. Although the enhanced cutoff frequency of the
strained Si MOSFET can facilitate the RF CMOS circuit design, the unintentionally induced threading dislocations in the strained Si channel can potentially degrade some RF circuits. Enhanced drive currents of 15 to 25% have
been demonstrated on sub-100 nm bulk strained silicon MOSFETs. However,
it has been difficult to implement because of misfit and threading dislocations, Ge outdiffusion, silicide formation difficulty, self-heating effect, higher
arsenic diffusion in the S/D extension region, and cost.