40
Strain-Engineered MOSFETs
flexibility is limited for applications involving a low Ge concentration
(in the buffer layer in the case of strained Si), a thinner active layer, and
relatively low process temperature windows. Incorporating smaller-size
carbon atoms substitutionally into the SiGe system enables one to compensate the strain, which leads to an increase in thermal stability and critical layer thickness. Growth of strain-compensated ternary SiGe:C layers
and relaxed buffer layers (as a template for growing strained Si) has been
reported by many researchers [2].
Incorporation of carbon has paved the way to extending SiGe-based
heterostructures, allowing more flexibility in strain and band gap engineering. Carbon-containing alloys promise to expand the range of device
applications of silicon-based heterostructures. It has been shown that carbon reduces the strain in SiGe at a faster rate than it increases the band
gap. Thus for a given band gap, a larger critical thickness can be obtained
for Si 1–x Ge x C y films than for those without carbon. The extracted valence
band offset in Si 1–x Ge x C y heterostructures also decreases much more slowly
than predicted with increasing carbon in the alloy, so that for a given lattice mismatch to Si, the valence band offset is larger for SiGe:C than for Si.
Therefore, both the band alignment and the valence band offset in ternary alloys are favourable for various device applications, as they reduce
the possibility of process-induced strain relaxation, while confining the
holes in the valence band quantum well. Partially strain compensated
Si 0.793 Ge 0.2 C 0.007 p-MOSFET devices have been fabricated using UHVCVD
grown layers [10]. The devices show good linear and saturation characteristics. Enhanced performance of ternary devices at room temperature has
been reported. The ternary device, however, shows a lower mobility at 77 K
than the binary device due to increased alloy and surface roughness scattering. The alloy scattering potential and field-dependent mobility degradation factor of the ternary SiGe:C layer have been estimated.
2.9 Strained Si MOSFETs
While biaxially compressed Si 1–x Ge x offers many desirable properties, most
of the advantages are encountered in the valence band causing an enhancement in hole mobility. To realise improvements in electron mobility and a
usable conduction band offset, it is necessary for the material to be in biaxial
tension. As discussed earlier, a smaller lattice constant Si epilayer will be
in biaxial tension when grown on a relaxed Si 1–x Ge x with larger lattice constant. In this case, type II band offset occurs and the structure has several
advantages over the more common type I band alignment, as a large band
offset (on the order of 100 meV or more) is obtained in both the conduction
and valence bands, relative to the relaxed Si 1–x Ge x layer. Strained Si provides
Strain-Engineered MOSFETs
flexibility is limited for applications involving a low Ge concentration
(in the buffer layer in the case of strained Si), a thinner active layer, and
relatively low process temperature windows. Incorporating smaller-size
carbon atoms substitutionally into the SiGe system enables one to compensate the strain, which leads to an increase in thermal stability and critical layer thickness. Growth of strain-compensated ternary SiGe:C layers
and relaxed buffer layers (as a template for growing strained Si) has been
reported by many researchers [2].
Incorporation of carbon has paved the way to extending SiGe-based
heterostructures, allowing more flexibility in strain and band gap engineering. Carbon-containing alloys promise to expand the range of device
applications of silicon-based heterostructures. It has been shown that carbon reduces the strain in SiGe at a faster rate than it increases the band
gap. Thus for a given band gap, a larger critical thickness can be obtained
for Si 1–x Ge x C y films than for those without carbon. The extracted valence
band offset in Si 1–x Ge x C y heterostructures also decreases much more slowly
than predicted with increasing carbon in the alloy, so that for a given lattice mismatch to Si, the valence band offset is larger for SiGe:C than for Si.
Therefore, both the band alignment and the valence band offset in ternary alloys are favourable for various device applications, as they reduce
the possibility of process-induced strain relaxation, while confining the
holes in the valence band quantum well. Partially strain compensated
Si 0.793 Ge 0.2 C 0.007 p-MOSFET devices have been fabricated using UHVCVD
grown layers [10]. The devices show good linear and saturation characteristics. Enhanced performance of ternary devices at room temperature has
been reported. The ternary device, however, shows a lower mobility at 77 K
than the binary device due to increased alloy and surface roughness scattering. The alloy scattering potential and field-dependent mobility degradation factor of the ternary SiGe:C layer have been estimated.
2.9 Strained Si MOSFETs
While biaxially compressed Si 1–x Ge x offers many desirable properties, most
of the advantages are encountered in the valence band causing an enhancement in hole mobility. To realise improvements in electron mobility and a
usable conduction band offset, it is necessary for the material to be in biaxial
tension. As discussed earlier, a smaller lattice constant Si epilayer will be
in biaxial tension when grown on a relaxed Si 1–x Ge x with larger lattice constant. In this case, type II band offset occurs and the structure has several
advantages over the more common type I band alignment, as a large band
offset (on the order of 100 meV or more) is obtained in both the conduction
and valence bands, relative to the relaxed Si 1–x Ge x layer. Strained Si provides